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drm/i915: use REG_BIT on FW_BLC_SELF_* macros

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Use REG_BIT() instead of open coding the shift in the FW_BLC_SELF_*
macro definitions to avoid potentially typing them as 'int'.

For example, this happens when we pass them to _MASKED_BIT_ENABLE(),
because of the typeof() construct there.  When we pass 1 << 15 (the
FW_BLC_SELF_EN macro), we get typeof(1 << 15), which is 'int'.  Then
the value becomes negative (-2147450880) and we try to assign it to a
'u32'.

In practice this is not a problem though, because when we try to
assign -2147450880 to the u32, that becomes 0x80008000, which was the
intended result.

Link: https://lore.kernel.org/intel-gfx/20250827111109.401604-1-luciano.coelho@intel.com/
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Luca Coelho 2025-08-27 13:12:06 +03:00
parent e9a1d54ed9
commit a304609be2
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/i915_reg.h
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@ -412,9 +412,9 @@
#define FW_BLC _MMIO(0x20d8)
#define FW_BLC2 _MMIO(0x20dc)
#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
#define FW_BLC_SELF_EN_MASK (1 << 31)
#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
#define FW_BLC_SELF_EN_MASK REG_BIT(31)
#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
#define MM_BURST_LENGTH 0x00700000
#define MM_FIFO_WATERMARK 0x0001F000
#define LM_BURST_LENGTH 0x00000700