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ASoC: add CS42L84 codec driver
Merge series from James Calligeros <jcalligeros99@gmail.com>: This patch set adds a driver for the Cirrus Logic CS42L84 codec. This chip is (so far) found only on Apple Silicon Macs. In keeping with proud Apple tradition, the CS42L84 is essentially just a CS42L42 with a different regmap and no publicly available datasheet. It may also be missing its parent's S/PDIF capabilities as none of Apple's devices support S/PDIF out, however this cannot be positively confirmed. This driver has lived in the downstream Asahi tree for quite a while now, and gained some refinements along the way. I have squashed most of these into the initial driver commit as they were small changes like tweaking msleep()s or filling out TLVs, but left seperate a larger change to tip/ring sense IRQ handling as it differs significantly from what is found in the CS42L42 driver.
This commit is contained in:
Mark Brown
commit
a2f4b8c860
56
Documentation/devicetree/bindings/sound/cirrus,cs42l84.yaml
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56
Documentation/devicetree/bindings/sound/cirrus,cs42l84.yaml
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@ -0,0 +1,56 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/cirrus,cs42l84.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cirrus Logic CS42L84 audio CODEC
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maintainers:
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- Martin Povišer <povik+lin@cutebit.org>
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description: |
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The CS42L84 is a headphone jack codec made by Cirrus Logic and embedded
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in personal computers sold by Apple. It was first seen in 2021 Macbook
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Pro models. It has stereo DAC for playback, mono ADC for capture, and
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is somewhat similar to CS42L42 but with a different regmap.
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properties:
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compatible:
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enum:
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- cirrus,cs42l84
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reg:
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maxItems: 1
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reset-gpios:
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maxItems: 1
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interrupts:
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maxItems: 1
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'#sound-dai-cells':
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const: 0
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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jack_codec: codec@4b {
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compatible = "cirrus,cs42l84";
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reg = <0x4b>;
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reset-gpios = <&pinctrl_nub 4 GPIO_ACTIVE_LOW>;
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interrupts-extended = <&pinctrl_ap 180 IRQ_TYPE_LEVEL_LOW>;
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#sound-dai-cells = <0>;
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};
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};
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@ -2132,9 +2132,11 @@ L: asahi@lists.linux.dev
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L: linux-sound@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/sound/adi,ssm3515.yaml
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F: Documentation/devicetree/bindings/sound/cirrus,cs42l84.yaml
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F: Documentation/devicetree/bindings/sound/apple,*
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F: sound/soc/apple/*
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F: sound/soc/codecs/cs42l83-i2c.c
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F: sound/soc/codecs/cs42l84.*
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F: sound/soc/codecs/ssm3515.c
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ARM/APPLE MACHINE SUPPORT
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@ -85,6 +85,7 @@ config SND_SOC_ALL_CODECS
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imply SND_SOC_CS42L52
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imply SND_SOC_CS42L56
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imply SND_SOC_CS42L73
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imply SND_SOC_CS42L84
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imply SND_SOC_CS4234
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imply SND_SOC_CS4265
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imply SND_SOC_CS4270
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@ -929,6 +930,12 @@ config SND_SOC_CS42L83
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select REGMAP_I2C
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select SND_SOC_CS42L42_CORE
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config SND_SOC_CS42L84
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tristate "Cirrus Logic CS42L84 CODEC"
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depends on I2C
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select REGMAP
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select REGMAP_I2C
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config SND_SOC_CS4234
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tristate "Cirrus Logic CS4234 CODEC"
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depends on I2C
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@ -91,6 +91,7 @@ snd-soc-cs42l52-y := cs42l52.o
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snd-soc-cs42l56-y := cs42l56.o
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snd-soc-cs42l73-y := cs42l73.o
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snd-soc-cs42l83-i2c-y := cs42l83-i2c.o
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snd-soc-cs42l84-objs := cs42l84.o
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snd-soc-cs4234-y := cs4234.o
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snd-soc-cs4265-y := cs4265.o
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snd-soc-cs4270-y := cs4270.o
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@ -505,6 +506,7 @@ obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
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obj-$(CONFIG_SND_SOC_CS42L56) += snd-soc-cs42l56.o
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obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
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obj-$(CONFIG_SND_SOC_CS42L83) += snd-soc-cs42l83-i2c.o
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obj-$(CONFIG_SND_SOC_CS42L84) += snd-soc-cs42l84.o
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obj-$(CONFIG_SND_SOC_CS4234) += snd-soc-cs4234.o
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obj-$(CONFIG_SND_SOC_CS4265) += snd-soc-cs4265.o
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obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
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1112
sound/soc/codecs/cs42l84.c
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1112
sound/soc/codecs/cs42l84.c
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File diff suppressed because it is too large
Load Diff
210
sound/soc/codecs/cs42l84.h
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210
sound/soc/codecs/cs42l84.h
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@ -0,0 +1,210 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) The Asahi Linux Contributors
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*
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* Based on sound/soc/codecs/cs42l42.h
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*
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* Copyright 2016 Cirrus Logic, Inc.
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*/
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#ifndef __CS42L84_H__
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#define __CS42L84_H__
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#include <linux/bits.h>
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#define CS42L84_CHIP_ID 0x42a84
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#define CS42L84_DEVID 0x0000
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#define CS42L84_REVID 0x73fe
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#define CS42L84_FRZ_CTL 0x0006
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#define CS42L84_FRZ_CTL_ENGAGE BIT(0)
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#define CS42L84_TSRS_PLUG_INT_STATUS 0x0400
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#define CS42L84_TSRS_PLUG_INT_MASK 0x0418
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#define CS42L84_RS_PLUG_SHIFT 0
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#define CS42L84_RS_PLUG BIT(0)
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#define CS42L84_RS_UNPLUG BIT(1)
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#define CS42L84_TS_PLUG_SHIFT 2
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#define CS42L84_TS_PLUG BIT(2)
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#define CS42L84_TS_UNPLUG BIT(3)
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#define CS42L84_TSRS_PLUG_VAL_MASK GENMASK(3, 0)
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#define CS42L84_PLL_LOCK_STATUS 0x040e // probably bit 0x10
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#define CS42L84_PLL_LOCK_STATUS_LOCKED BIT(4)
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#define CS42L84_PLL_LOCK_STATUS_ERROR BIT(5)
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#define CS42L84_PLUG 3
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#define CS42L84_UNPLUG 0
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#define CS42L84_TRANS 1
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#define CS42L84_CCM_CTL1 0x0600
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#define CS42L84_CCM_CTL1_MCLK_SRC GENMASK(1, 0)
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#define CS42L84_CCM_CTL1_MCLK_SRC_RCO 0
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#define CS42L84_CCM_CTL1_MCLK_SRC_MCLK 1
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#define CS42L84_CCM_CTL1_MCLK_SRC_BCLK 2
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#define CS42L84_CCM_CTL1_MCLK_SRC_PLL 3
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#define CS42L84_CCM_CTL1_MCLK_FREQ GENMASK(3, 2)
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#define CS42L84_CCM_CTL1_MCLK_F_12MHZ 0b00
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#define CS42L84_CCM_CTL1_MCLK_F_24MHZ 0b01
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#define CS42L84_CCM_CTL1_MCLK_F_12_288KHZ 0b10
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#define CS42L84_CCM_CTL1_MCLK_F_24_576KHZ 0b11
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#define CS42L84_CCM_CTL1_RCO \
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(FIELD_PREP(CS42L84_CCM_CTL1_MCLK_SRC, CS42L84_CCM_CTL1_MCLK_SRC_RCO) \
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| FIELD_PREP(CS42L84_CCM_CTL1_MCLK_FREQ, CS42L84_CCM_CTL1_MCLK_F_12MHZ))
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#define CS42L84_CCM_SAMP_RATE 0x0601
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#define CS42L84_CCM_SAMP_RATE_RATE_48KHZ 4
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#define CS42L84_CCM_SAMP_RATE_RATE_96KHZ 5
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#define CS42L84_CCM_SAMP_RATE_RATE_192KHZ 6
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#define CS42L84_CCM_SAMP_RATE_RATE_44K1HZ 12
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#define CS42L84_CCM_SAMP_RATE_RATE_88K2HZ 13
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#define CS42L84_CCM_SAMP_RATE_RATE_176K4HZ 14
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#define CS42L84_CCM_CTL3 0x0602
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#define CS42L84_CCM_CTL3_REFCLK_DIV GENMASK(2, 1)
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#define CS42L84_CCM_CTL4 0x0603
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#define CS42L84_CCM_CTL4_REFCLK_EN BIT(0)
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#define CS42L84_CCM_ASP_CLK_CTRL 0x0608
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#define CS42L84_PLL_CTL1 0x0800
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#define CS42L84_PLL_CTL1_EN BIT(0)
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#define CS42L84_PLL_CTL1_MODE GENMASK(2, 1)
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#define CS42L84_PLL_DIV_FRAC0 0x0804
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#define CS42L84_PLL_DIV_FRAC1 0x0805
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#define CS42L84_PLL_DIV_FRAC2 0x0806
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#define CS42L84_PLL_DIV_INT 0x0807
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#define CS42L84_PLL_DIVOUT 0x0808
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#define CS42L84_RING_SENSE_CTL 0x1282
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#define CS42L84_RING_SENSE_CTL_INV BIT(7)
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#define CS42L84_RING_SENSE_CTL_UNK1 BIT(6)
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#define CS42L84_RING_SENSE_CTL_FALLTIME GENMASK(5, 3)
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#define CS42L84_RING_SENSE_CTL_RISETIME GENMASK(2, 0)
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#define CS42L84_TIP_SENSE_CTL 0x1283
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#define CS42L84_TIP_SENSE_CTL_INV BIT(7)
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#define CS42L84_TIP_SENSE_CTL_FALLTIME GENMASK(5, 3)
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#define CS42L84_TIP_SENSE_CTL_RISETIME GENMASK(2, 0)
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#define CS42L84_TSRS_PLUG_STATUS 0x1288
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#define CS42L84_TIP_SENSE_CTL2 0x1473
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#define CS42L84_TIP_SENSE_CTL2_MODE GENMASK(7, 6)
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#define CS42L84_TIP_SENSE_CTL2_MODE_DISABLED 0b00
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#define CS42L84_TIP_SENSE_CTL2_MODE_DIG_INPUT 0b01
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#define CS42L84_TIP_SENSE_CTL2_MODE_SHORT_DET 0b11
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#define CS42L84_TIP_SENSE_CTL2_INV BIT(5)
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#define CS42L84_MISC_DET_CTL 0x1474
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#define CS42L84_MISC_DET_CTL_DETECT_MODE GENMASK(4, 3)
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#define CS42L84_MISC_DET_CTL_HSBIAS_CTL GENMASK(2, 1)
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#define CS42L84_MISC_DET_CTL_PDN_MIC_LVL_DET BIT(0)
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#define CS42L84_MIC_DET_CTL1 0x1475
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#define CS42L84_MIC_DET_CTL1_HS_DET_LEVEL GENMASK(5, 0)
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#define CS42L84_MIC_DET_CTL4 0x1477
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#define CS42L84_MIC_DET_CTL4_LATCH_TO_VP BIT(1)
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#define CS42L84_HS_DET_STATUS2 0x147d
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#define CS42L84_MSM_BLOCK_EN1 0x1800
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#define CS42L84_MSM_BLOCK_EN2 0x1801
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#define CS42L84_MSM_BLOCK_EN2_ASP_SHIFT 6
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#define CS42L84_MSM_BLOCK_EN2_BUS_SHIFT 5
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#define CS42L84_MSM_BLOCK_EN2_DAC_SHIFT 4
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#define CS42L84_MSM_BLOCK_EN2_ADC_SHIFT 3
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#define CS42L84_MSM_BLOCK_EN3 0x1802
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#define CS42L84_MSM_BLOCK_EN3_TR_SENSE BIT(3)
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#define CS42L84_HS_DET_CTL2 0x1811
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#define CS42L84_HS_DET_CTL2_CTL GENMASK(7, 6)
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#define CS42L84_HS_DET_CTL2_SET GENMASK(5, 4)
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#define CS42L84_HS_DET_CTL2_REF BIT(3)
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#define CS42L84_HS_DET_CTL2_AUTO_TIME GENMASK(1, 0)
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#define CS42L84_HS_SWITCH_CTL 0x1812
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#define CS42L84_HS_SWITCH_CTL_REF_HS3 BIT(7)
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#define CS42L84_HS_SWITCH_CTL_REF_HS4 BIT(6)
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#define CS42L84_HS_SWITCH_CTL_HSB_FILT_HS3 BIT(5)
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#define CS42L84_HS_SWITCH_CTL_HSB_FILT_HS4 BIT(4)
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#define CS42L84_HS_SWITCH_CTL_HSB_HS3 BIT(3)
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#define CS42L84_HS_SWITCH_CTL_HSB_HS4 BIT(2)
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#define CS42L84_HS_SWITCH_CTL_GNDHS_HS3 BIT(1)
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#define CS42L84_HS_SWITCH_CTL_GNDHS_HS4 BIT(0)
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#define CS42L84_HS_CLAMP_DISABLE 0x1813
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#define CS42L84_ADC_CTL1 0x2000
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#define CS42L84_ADC_CTL1_PREAMP_GAIN_SHIFT 6
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#define CS42L84_ADC_CTL1_PGA_GAIN_SHIFT 0
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#define CS42L84_ADC_CTL4 0x2003
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#define CS42L84_ADC_CTL4_WNF_CF_SHIFT 4
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#define CS42L84_ADC_CTL4_WNF_EN_SHIFT 3
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#define CS42L84_ADC_CTL4_HPF_CF_SHIFT 1
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#define CS42L84_ADC_CTL4_HPF_EN_SHIFT 0
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#define CS42L84_DAC_CTL1 0x3000
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#define CS42L84_DAC_CTL1_UNMUTE BIT(0)
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//#define CS42L84_DAC_CTL1_DACB_INV_SHIFT 1
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//#define CS42L84_DAC_CTL1_DACA_INV_SHIFT 0
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#define CS42L84_DAC_CTL2 0x3001
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#define CS42L84_DAC_CHA_VOL_LSB 0x3004
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#define CS42L84_DAC_CHA_VOL_MSB 0x3005
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#define CS42L84_DAC_CHB_VOL_LSB 0x3006
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#define CS42L84_DAC_CHB_VOL_MSB 0x3007
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#define CS42L84_HP_VOL_CTL 0x3020
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#define CS42L84_HP_VOL_CTL_ZERO_CROSS BIT(1)
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#define CS42L84_HP_VOL_CTL_SOFT BIT(0)
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#define CS42L84_SRC_ASP_RX_CH1 0b1101
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#define CS42L84_SRC_ASP_RX_CH2 0b1110
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#define CS42L84_BUS_ASP_TX_SRC 0x4000
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#define CS42L84_BUS_ASP_TX_SRC_CH1_SHIFT 0
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#define CS42L84_BUS_DAC_SRC 0x4001
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#define CS42L84_BUS_DAC_SRC_DACA_SHIFT 0
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#define CS42L84_BUS_DAC_SRC_DACB_SHIFT 4
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#define CS42L84_ASP_CTL 0x5000
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#define CS42L84_ASP_CTL_BCLK_EN_SHIFT 1
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#define CS42L84_ASP_CTL_TDM_MODE BIT(2)
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#define CS42L84_ASP_FSYNC_CTL2 0x5010
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#define CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO GENMASK(7, 1)
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#define CS42L84_ASP_FSYNC_CTL3 0x5011
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#define CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI GENMASK(4, 0)
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#define CS42L84_ASP_DATA_CTL 0x5018
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#define CS42L84_ASP_RX_EN 0x5020
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#define CS42L84_ASP_RX_EN_CH1_SHIFT 0
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#define CS42L84_ASP_RX_EN_CH2_SHIFT 1
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#define CS42L84_ASP_TX_EN 0x5024
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#define CS42L84_ASP_TX_EN_CH1_SHIFT 0
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#define CS42L84_ASP_RX_CH1_CTL1 0x5028
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#define CS42L84_ASP_RX_CH1_CTL2 0x5029
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#define CS42L84_ASP_RX_CH1_WIDTH 0x502a
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#define CS42L84_ASP_RX_CH2_CTL1 0x502c
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#define CS42L84_ASP_RX_CH2_CTL2 0x502d
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#define CS42L84_ASP_RX_CH2_WIDTH 0x502e
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#define CS42L84_ASP_RX_CHx_CTL1_EDGE BIT(0)
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#define CS42L84_ASP_RX_CHx_CTL1_SLOT_START_LSB GENMASK(7, 1)
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#define CS42L84_ASP_RX_CHx_CTL2_SLOT_START_MSB GENMASK(2, 0)
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#define CS42L84_ASP_TX_CH1_CTL1 0x5068
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#define CS42L84_ASP_TX_CH1_CTL2 0x5069
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#define CS42L84_ASP_TX_CH1_WIDTH 0x506a
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#define CS42L84_ASP_TX_CH2_CTL1 0x506c
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#define CS42L84_ASP_TX_CH2_CTL2 0x506d
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#define CS42L84_ASP_TX_CH2_WIDTH 0x506e
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#define CS42L84_DEBOUNCE_TIME_125MS 0b001
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#define CS42L84_DEBOUNCE_TIME_500MS 0b011
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#define CS42L84_BOOT_TIME_US 3000
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#define CS42L84_CLOCK_SWITCH_DELAY_US 150
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#define CS42L84_PLL_LOCK_POLL_US 250
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#define CS42L84_PLL_LOCK_TIMEOUT_US 1250
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#endif /* __CS42L84_H__ */
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