mirror of
https://github.com/torvalds/linux.git
synced 2026-06-04 04:23:35 +02:00
Merge branches 'clk-kunit', 'clk-mediatek', 'clk-cleanup' and 'clk-bindings' into clk-next
- KUnit tests for clk registration and fixed rate basic clk type * clk-kunit: clk: Add KUnit tests for clks registered with struct clk_parent_data clk: Add KUnit tests for clk fixed rate basic type clk: Add test managed clk provider/consumer APIs platform: Add test managed platform_device/driver APIs of: Add a KUnit test for overlays and test managed APIs dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends of: Add test managed wrappers for of_overlay_apply()/of_node_put() of/platform: Allow overlays to create platform devices from the root node * clk-mediatek: dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema dt-bindings: Move Mediatek clock controllers to "clock" directory dt-bindings: clock: mediatek,apmixedsys: Fix "mediatek,mt6779-apmixed" compatible clk: mediatek: reset: Remove unused mtk_register_reset_controller() clk: mediatek: reset: Return regmap's error code * clk-cleanup: clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: ti: dra7-atl: Fix leak of of_nodes clk:davinci: make use of dev_err_cast_probe() clk: bcm: bcm53573: fix OF node leak in init clk: lmk04832: Use devm_clk_get_enabled() helpers clk: visconti: Switch to use kmemdup_array() clk: mmp: Switch to use kmemdup_array() clk: hisilicon: Remove unnecessary local variable clk: use clk_core_unlink_consumer() helper clk: Use of_property_present() clk: at91: Use of_property_count_u32_elems() to get property length da8xx-cfgchip.c: replace of_node_put with __free improves cleanup * clk-bindings: dt-bindings: clock: st,stm32mp1-rcc: add top-level constraints dt-bindings: clock: cirrus,lochnagar: add top-level constraints dt-bindings: clock: baikal,bt1-ccu-div: add top-level constraints dt-bindings: clock: nxp,lpc3220-usb-clk: Convert bindings to dtschema dt-bindings: clock: nxp,lpc3220-clk: Convert bindings to DT schema
This commit is contained in:
Stephen Boyd
commit
a2b88026f7
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@ -1,24 +0,0 @@
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Mediatek bdpsys controller
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============================
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|
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The Mediatek bdpsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-bdpsys", "syscon"
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- "mediatek,mt2712-bdpsys", "syscon"
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- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
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- #clock-cells: Must be 1
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The bdpsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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bdpsys: clock-controller@1c000000 {
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compatible = "mediatek,mt2701-bdpsys", "syscon";
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reg = <0 0x1c000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,24 +0,0 @@
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MediaTek CAMSYS controller
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============================
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The MediaTek camsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6765-camsys", "syscon"
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- "mediatek,mt6779-camsys", "syscon"
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- "mediatek,mt8183-camsys", "syscon"
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- #clock-cells: Must be 1
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The camsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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camsys: camsys@1a000000 {
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compatible = "mediatek,mt8183-camsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,30 +0,0 @@
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Mediatek imgsys controller
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============================
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The Mediatek imgsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6765-imgsys", "syscon"
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- "mediatek,mt6779-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8167-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- "mediatek,mt8183-imgsys", "syscon"
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- #clock-cells: Must be 1
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The imgsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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imgsys: clock-controller@15000000 {
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compatible = "mediatek,mt8173-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,22 +0,0 @@
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Mediatek ipesys controller
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============================
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The Mediatek ipesys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt6779-ipesys", "syscon"
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- #clock-cells: Must be 1
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The ipesys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ipesys: clock-controller@1b000000 {
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compatible = "mediatek,mt6779-ipesys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,43 +0,0 @@
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Mediatek IPU controller
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============================
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The Mediatek ipu controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt8183-ipu_conn", "syscon"
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- "mediatek,mt8183-ipu_adl", "syscon"
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- "mediatek,mt8183-ipu_core0", "syscon"
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- "mediatek,mt8183-ipu_core1", "syscon"
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- #clock-cells: Must be 1
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The ipu controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ipu_conn: syscon@19000000 {
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compatible = "mediatek,mt8183-ipu_conn", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_adl: syscon@19010000 {
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compatible = "mediatek,mt8183-ipu_adl", "syscon";
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reg = <0 0x19010000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core0: syscon@19180000 {
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compatible = "mediatek,mt8183-ipu_core0", "syscon";
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reg = <0 0x19180000 0 0x1000>;
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#clock-cells = <1>;
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};
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ipu_core1: syscon@19280000 {
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compatible = "mediatek,mt8183-ipu_core1", "syscon";
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reg = <0 0x19280000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,22 +0,0 @@
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Mediatek jpgdecsys controller
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============================
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The Mediatek jpgdecsys controller provides various clocks to the system.
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|
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Required Properties:
|
||||
|
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- compatible: Should be:
|
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- "mediatek,mt2712-jpgdecsys", "syscon"
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- #clock-cells: Must be 1
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|
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The jpgdecsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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jpgdecsys: syscon@19000000 {
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compatible = "mediatek,mt2712-jpgdecsys", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,23 +0,0 @@
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Mediatek mcucfg controller
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============================
|
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|
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The Mediatek mcucfg controller provides various clocks to the system.
|
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|
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Required Properties:
|
||||
|
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- compatible: Should be one of:
|
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- "mediatek,mt2712-mcucfg", "syscon"
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- "mediatek,mt8183-mcucfg", "syscon"
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- #clock-cells: Must be 1
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The mcucfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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mcucfg: syscon@10220000 {
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compatible = "mediatek,mt2712-mcucfg", "syscon";
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reg = <0 0x10220000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,25 +0,0 @@
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Mediatek mfgcfg controller
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============================
|
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|
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The Mediatek mfgcfg controller provides various clocks to the system.
|
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|
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Required Properties:
|
||||
|
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- compatible: Should be one of:
|
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- "mediatek,mt2712-mfgcfg", "syscon"
|
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- "mediatek,mt6779-mfgcfg", "syscon"
|
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- "mediatek,mt8167-mfgcfg", "syscon"
|
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- "mediatek,mt8183-mfgcfg", "syscon"
|
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- #clock-cells: Must be 1
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|
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The mfgcfg controller uses the common clk binding from
|
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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mfgcfg: syscon@13000000 {
|
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compatible = "mediatek,mt2712-mfgcfg", "syscon";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -1,28 +0,0 @@
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Mediatek mipi0a (mipi_rx_ana_csi0a) controller
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||||
============================
|
||||
|
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The Mediatek mipi0a controller provides various clocks
|
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to the system.
|
||||
|
||||
Required Properties:
|
||||
|
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- compatible: Should be one of:
|
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- "mediatek,mt6765-mipi0a", "syscon"
|
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- #clock-cells: Must be 1
|
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|
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The mipi0a controller uses the common clk binding from
|
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Documentation/devicetree/bindings/clock/clock-bindings.txt
|
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
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The mipi0a controller also uses the common power domain from
|
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Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power domains are defined in dt-bindings/power/mt*-power.h.
|
||||
|
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Example:
|
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mipi0a: clock-controller@11c10000 {
|
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compatible = "mediatek,mt6765-mipi0a", "syscon";
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reg = <0 0x11c10000 0 0x1000>;
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power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
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#clock-cells = <1>;
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};
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|
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@ -1,27 +0,0 @@
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Mediatek vcodecsys controller
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============================
|
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|
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The Mediatek vcodecsys controller provides various clocks to the system.
|
||||
|
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Required Properties:
|
||||
|
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- compatible: Should be one of:
|
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- "mediatek,mt6765-vcodecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vcodecsys controller uses the common clk binding from
|
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Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The vcodecsys controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power domains are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
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venc_gcon: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
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reg = <0 0x17000000 0 0x10000>;
|
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power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
|
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#clock-cells = <1>;
|
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};
|
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|
|
@ -1,29 +0,0 @@
|
|||
Mediatek vdecsys controller
|
||||
============================
|
||||
|
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The Mediatek vdecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt2712-vdecsys", "syscon"
|
||||
- "mediatek,mt6779-vdecsys", "syscon"
|
||||
- "mediatek,mt6797-vdecsys", "syscon"
|
||||
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
|
||||
- "mediatek,mt8167-vdecsys", "syscon"
|
||||
- "mediatek,mt8173-vdecsys", "syscon"
|
||||
- "mediatek,mt8183-vdecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vdecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vdecsys: clock-controller@16000000 {
|
||||
compatible = "mediatek,mt8173-vdecsys", "syscon";
|
||||
reg = <0 0x16000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Mediatek vencltsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vencltsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be:
|
||||
- "mediatek,mt8173-vencltsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vencltsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vencltsys: clock-controller@19000000 {
|
||||
compatible = "mediatek,mt8173-vencltsys", "syscon";
|
||||
reg = <0 0x19000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
Mediatek vencsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vencsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2712-vencsys", "syscon"
|
||||
- "mediatek,mt6779-vencsys", "syscon"
|
||||
- "mediatek,mt6797-vencsys", "syscon"
|
||||
- "mediatek,mt8173-vencsys", "syscon"
|
||||
- "mediatek,mt8183-vencsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vencsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
vencsys: clock-controller@18000000 {
|
||||
compatible = "mediatek,mt8173-vencsys", "syscon";
|
||||
reg = <0 0x18000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -134,9 +134,13 @@ properties:
|
|||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks: true
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
clock-names: true
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
clocks: true
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ properties:
|
|||
- mediatek,mt2701-apmixedsys
|
||||
- mediatek,mt2712-apmixedsys
|
||||
- mediatek,mt6765-apmixedsys
|
||||
- mediatek,mt6779-apmixedsys
|
||||
- mediatek,mt6779-apmixed
|
||||
- mediatek,mt6795-apmixedsys
|
||||
- mediatek,mt7629-apmixedsys
|
||||
- mediatek,mt8167-apmixedsys
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Infrastructure System Configuration Controller
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8186
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8186
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8192
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8192
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8195
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8195
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,pericfg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Peripheral Configuration Controller
|
||||
93
Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
Normal file
93
Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,syscon.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Clock controller syscon's
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
|
||||
description:
|
||||
The MediaTek clock controller syscon's provide various clocks to the system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-bdpsys
|
||||
- mediatek,mt2701-imgsys
|
||||
- mediatek,mt2701-vdecsys
|
||||
- mediatek,mt2712-bdpsys
|
||||
- mediatek,mt2712-imgsys
|
||||
- mediatek,mt2712-jpgdecsys
|
||||
- mediatek,mt2712-mcucfg
|
||||
- mediatek,mt2712-mfgcfg
|
||||
- mediatek,mt2712-vdecsys
|
||||
- mediatek,mt2712-vencsys
|
||||
- mediatek,mt6765-camsys
|
||||
- mediatek,mt6765-imgsys
|
||||
- mediatek,mt6765-mipi0a
|
||||
- mediatek,mt6765-vcodecsys
|
||||
- mediatek,mt6779-camsys
|
||||
- mediatek,mt6779-imgsys
|
||||
- mediatek,mt6779-ipesys
|
||||
- mediatek,mt6779-mfgcfg
|
||||
- mediatek,mt6779-vdecsys
|
||||
- mediatek,mt6779-vencsys
|
||||
- mediatek,mt6797-imgsys
|
||||
- mediatek,mt6797-vdecsys
|
||||
- mediatek,mt6797-vencsys
|
||||
- mediatek,mt8167-imgsys
|
||||
- mediatek,mt8167-mfgcfg
|
||||
- mediatek,mt8167-vdecsys
|
||||
- mediatek,mt8173-imgsys
|
||||
- mediatek,mt8173-vdecsys
|
||||
- mediatek,mt8173-vencltsys
|
||||
- mediatek,mt8173-vencsys
|
||||
- mediatek,mt8183-camsys
|
||||
- mediatek,mt8183-imgsys
|
||||
- mediatek,mt8183-ipu_conn
|
||||
- mediatek,mt8183-ipu_adl
|
||||
- mediatek,mt8183-ipu_core0
|
||||
- mediatek,mt8183-ipu_core1
|
||||
- mediatek,mt8183-mcucfg
|
||||
- mediatek,mt8183-mfgcfg
|
||||
- mediatek,mt8183-vdecsys
|
||||
- mediatek,mt8183-vencsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-bdpsys
|
||||
- const: mediatek,mt2701-bdpsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-imgsys
|
||||
- const: mediatek,mt2701-imgsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-vdecsys
|
||||
- const: mediatek,mt2701-vdecsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11220000 {
|
||||
compatible = "mediatek,mt2701-bdpsys", "syscon";
|
||||
reg = <0x11220000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
NXP LPC32xx Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
clock controller
|
||||
- clocks: phandles of external oscillators, the list must contain one
|
||||
32768 Hz oscillator and may have one optional high frequency oscillator
|
||||
- clock-names: list of external oscillator clock names, must contain
|
||||
"xtal_32k" and may have optional "xtal"
|
||||
|
||||
Examples:
|
||||
|
||||
/* System Control Block */
|
||||
scb {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x040004000 0x00001000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clk: clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
};
|
||||
51
Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.yaml
Normal file
51
Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.yaml
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP LPC32xx Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Animesh Agarwal <animeshagarwal28@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,lpc3220-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: External 32768 Hz oscillator.
|
||||
- description: Optional high frequency oscillator.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xtal_32k
|
||||
- const: xtal
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@0 {
|
||||
compatible = "nxp,lpc3220-clk";
|
||||
reg = <0x00 0x114>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal_32k>, <&xtal>;
|
||||
clock-names = "xtal_32k", "xtal";
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
NXP LPC32xx USB Clock Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "nxp,lpc3220-usb-clk"
|
||||
- reg: should contain clock controller registers location and length
|
||||
- #clock-cells: must be 1, the cell holds id of a clock provided by the
|
||||
USB clock controller
|
||||
|
||||
Examples:
|
||||
|
||||
usb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x31020000 0x00001000>;
|
||||
|
||||
usbclk: clock-controller@f00 {
|
||||
compatible = "nxp,lpc3220-usb-clk";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/nxp,lpc3220-usb-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP LPC32xx USB Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Animesh Agarwal <animeshagarwal28@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nxp,lpc3220-usb-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@f00 {
|
||||
compatible = "nxp,lpc3220-usb-clk";
|
||||
reg = <0xf00 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -60,8 +60,14 @@ properties:
|
|||
- st,stm32mp1-rcc
|
||||
- st,stm32mp13-rcc
|
||||
- const: syscon
|
||||
clocks: true
|
||||
clock-names: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -563,9 +563,10 @@ of_at91_clk_pll_get_characteristics(struct device_node *np)
|
|||
if (num_cells < 2 || num_cells > 4)
|
||||
return NULL;
|
||||
|
||||
if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
|
||||
num_output = of_property_count_u32_elems(np, "atmel,pll-clk-output-ranges");
|
||||
if (num_output <= 0)
|
||||
return NULL;
|
||||
num_output = tmp / (sizeof(u32) * num_cells);
|
||||
num_output /= num_cells;
|
||||
|
||||
characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
|
||||
if (!characteristics)
|
||||
|
|
|
|||
|
|
@ -112,7 +112,7 @@ static void bcm53573_ilp_init(struct device_node *np)
|
|||
goto err_free_ilp;
|
||||
}
|
||||
|
||||
ilp->regmap = syscon_node_to_regmap(of_get_parent(np));
|
||||
ilp->regmap = syscon_node_to_regmap(np->parent);
|
||||
if (IS_ERR(ilp->regmap)) {
|
||||
err = PTR_ERR(ilp->regmap);
|
||||
goto err_free_ilp;
|
||||
|
|
|
|||
|
|
@ -1405,16 +1405,12 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
|
||||
lmk->dev = &spi->dev;
|
||||
|
||||
lmk->oscin = devm_clk_get(lmk->dev, "oscin");
|
||||
lmk->oscin = devm_clk_get_enabled(lmk->dev, "oscin");
|
||||
if (IS_ERR(lmk->oscin)) {
|
||||
dev_err(lmk->dev, "failed to get oscin clock\n");
|
||||
return PTR_ERR(lmk->oscin);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(lmk->oscin);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
|
||||
GPIOD_OUT_LOW);
|
||||
|
||||
|
|
@ -1422,14 +1418,14 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
sizeof(struct lmk_dclk), GFP_KERNEL);
|
||||
if (!lmk->dclk) {
|
||||
ret = -ENOMEM;
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
|
||||
sizeof(*lmk->clkout), GFP_KERNEL);
|
||||
if (!lmk->clkout) {
|
||||
ret = -ENOMEM;
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
|
||||
|
|
@ -1437,7 +1433,7 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
GFP_KERNEL);
|
||||
if (!lmk->clk_data) {
|
||||
ret = -ENOMEM;
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
|
||||
|
|
@ -1465,7 +1461,7 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
dev_err(lmk->dev, "missing reg property in child: %s\n",
|
||||
child->full_name);
|
||||
of_node_put(child);
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
of_property_read_u32(child, "ti,clkout-fmt",
|
||||
|
|
@ -1486,7 +1482,7 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
|
||||
__func__, PTR_ERR(lmk->regmap));
|
||||
ret = PTR_ERR(lmk->regmap);
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
|
||||
|
|
@ -1496,7 +1492,7 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
&rdbk_pin);
|
||||
ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
|
||||
if (ret)
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
|
||||
|
|
@ -1504,13 +1500,13 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
|
||||
tmp[0] << 8 | tmp[1], tmp[2]);
|
||||
ret = -EINVAL;
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = lmk04832_register_vco(lmk);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to init device clock path\n");
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (lmk->vco_rate) {
|
||||
|
|
@ -1518,21 +1514,21 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to set VCO rate\n");
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = lmk04832_register_sclk(lmk);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < info->num_channels; i++) {
|
||||
ret = lmk04832_register_clkout(lmk, i);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to register clk %d\n", i);
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1541,24 +1537,12 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
lmk->clk_data);
|
||||
if (ret) {
|
||||
dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
|
||||
goto err_disable_oscin;
|
||||
return ret;
|
||||
}
|
||||
|
||||
spi_set_drvdata(spi, lmk);
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_oscin:
|
||||
clk_disable_unprepare(lmk->oscin);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void lmk04832_remove(struct spi_device *spi)
|
||||
{
|
||||
struct lmk04832 *lmk = spi_get_drvdata(spi);
|
||||
|
||||
clk_disable_unprepare(lmk->oscin);
|
||||
}
|
||||
|
||||
static const struct spi_device_id lmk04832_id[] = {
|
||||
|
|
@ -1579,7 +1563,6 @@ static struct spi_driver lmk04832_driver = {
|
|||
.of_match_table = lmk04832_of_id,
|
||||
},
|
||||
.probe = lmk04832_probe,
|
||||
.remove = lmk04832_remove,
|
||||
.id_table = lmk04832_id,
|
||||
};
|
||||
module_spi_driver(lmk04832_driver);
|
||||
|
|
|
|||
|
|
@ -4762,7 +4762,7 @@ void __clk_put(struct clk *clk)
|
|||
clk->exclusive_count = 0;
|
||||
}
|
||||
|
||||
hlist_del(&clk->clks_node);
|
||||
clk_core_unlink_consumer(clk);
|
||||
|
||||
/* If we had any boundaries on that clock, let's drop them. */
|
||||
if (clk->min_rate > 0 || clk->max_rate < ULONG_MAX)
|
||||
|
|
@ -5232,7 +5232,7 @@ static int of_parse_clkspec(const struct device_node *np, int index,
|
|||
* clocks.
|
||||
*/
|
||||
np = np->parent;
|
||||
if (np && !of_get_property(np, "clock-ranges", NULL))
|
||||
if (np && !of_property_present(np, "clock-ranges"))
|
||||
break;
|
||||
index = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -513,8 +513,7 @@ da8xx_cfgchip_register_usb0_clk48(struct device *dev,
|
|||
|
||||
fck_clk = devm_clk_get(dev, "fck");
|
||||
if (IS_ERR(fck_clk)) {
|
||||
dev_err_probe(dev, PTR_ERR(fck_clk), "Missing fck clock\n");
|
||||
return ERR_CAST(fck_clk);
|
||||
return dev_err_cast_probe(dev, fck_clk, "Missing fck clock\n");
|
||||
}
|
||||
|
||||
usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
|
||||
|
|
@ -749,11 +748,9 @@ static int da8xx_cfgchip_probe(struct platform_device *pdev)
|
|||
|
||||
clk_init = device_get_match_data(dev);
|
||||
if (clk_init) {
|
||||
struct device_node *parent;
|
||||
struct device_node *parent __free(device_node) = of_get_parent(dev->of_node);
|
||||
|
||||
parent = of_get_parent(dev->of_node);
|
||||
regmap = syscon_node_to_regmap(parent);
|
||||
of_node_put(parent);
|
||||
} else if (pdev->id_entry && pdata) {
|
||||
clk_init = (void *)pdev->id_entry->driver_data;
|
||||
regmap = pdata->cfgchip;
|
||||
|
|
|
|||
|
|
@ -407,7 +407,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
|
|||
unsigned long parent_rate)
|
||||
{
|
||||
struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
|
||||
u64 frac_val, fbdiv_val, refdiv_val;
|
||||
u64 frac_val, fbdiv_val;
|
||||
u32 postdiv1_val, postdiv2_val;
|
||||
u32 val;
|
||||
u64 tmp, rate;
|
||||
|
|
@ -435,14 +435,13 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
|
|||
val = readl_relaxed(clk->ctrl_reg2);
|
||||
val = val >> clk->refdiv_shift;
|
||||
val &= ((1 << clk->refdiv_width) - 1);
|
||||
refdiv_val = val;
|
||||
|
||||
/* rate = 24000000 * (fbdiv + frac / (1<<24) ) / refdiv */
|
||||
rate = 0;
|
||||
tmp = 24000000 * fbdiv_val + (24000000 * frac_val) / (1 << 24);
|
||||
rate += tmp;
|
||||
do_div(rate, refdiv_val);
|
||||
do_div(rate, postdiv1_val * postdiv2_val);
|
||||
rate = div_u64(rate, val);
|
||||
rate = div_u64(rate, postdiv1_val * postdiv2_val);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -110,65 +110,6 @@ static int reset_xlate(struct reset_controller_dev *rcdev,
|
|||
return data->desc->rst_idx_map[reset_spec->args[0]];
|
||||
}
|
||||
|
||||
int mtk_register_reset_controller(struct device_node *np,
|
||||
const struct mtk_clk_rst_desc *desc)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
const struct reset_control_ops *rcops = NULL;
|
||||
struct mtk_clk_rst_data *data;
|
||||
int ret;
|
||||
|
||||
if (!desc) {
|
||||
pr_err("mtk clock reset desc is NULL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (desc->version) {
|
||||
case MTK_RST_SIMPLE:
|
||||
rcops = &mtk_reset_ops;
|
||||
break;
|
||||
case MTK_RST_SET_CLR:
|
||||
rcops = &mtk_reset_ops_set_clr;
|
||||
break;
|
||||
default:
|
||||
pr_err("Unknown reset version %d\n", desc->version);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->desc = desc;
|
||||
data->regmap = regmap;
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.ops = rcops;
|
||||
data->rcdev.of_node = np;
|
||||
|
||||
if (data->desc->rst_idx_map_nr > 0) {
|
||||
data->rcdev.of_reset_n_cells = 1;
|
||||
data->rcdev.nr_resets = desc->rst_idx_map_nr;
|
||||
data->rcdev.of_xlate = reset_xlate;
|
||||
} else {
|
||||
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
|
||||
}
|
||||
|
||||
ret = reset_controller_register(&data->rcdev);
|
||||
if (ret) {
|
||||
pr_err("could not register reset controller: %d\n", ret);
|
||||
kfree(data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mtk_register_reset_controller_with_dev(struct device *dev,
|
||||
const struct mtk_clk_rst_desc *desc)
|
||||
{
|
||||
|
|
@ -198,7 +139,7 @@ int mtk_register_reset_controller_with_dev(struct device *dev,
|
|||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(dev, "Cannot find regmap %pe\n", regmap);
|
||||
return -EINVAL;
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
|
|
|
|||
|
|
@ -59,16 +59,6 @@ struct mtk_clk_rst_data {
|
|||
const struct mtk_clk_rst_desc *desc;
|
||||
};
|
||||
|
||||
/**
|
||||
* mtk_register_reset_controller - Register MediaTek clock reset controller
|
||||
* @np: Pointer to device node.
|
||||
* @desc: Constant pointer to description of clock reset.
|
||||
*
|
||||
* Return: 0 on success and errorno otherwise.
|
||||
*/
|
||||
int mtk_register_reset_controller(struct device_node *np,
|
||||
const struct mtk_clk_rst_desc *desc);
|
||||
|
||||
/**
|
||||
* mtk_register_reset_controller - Register mediatek clock reset controller with device
|
||||
* @np: Pointer to device.
|
||||
|
|
|
|||
|
|
@ -447,7 +447,6 @@ struct clk *mmp_clk_register_mix(struct device *dev,
|
|||
struct mmp_clk_mix *mix;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
size_t table_bytes;
|
||||
|
||||
mix = kzalloc(sizeof(*mix), GFP_KERNEL);
|
||||
if (!mix)
|
||||
|
|
@ -461,8 +460,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
|
|||
|
||||
memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
|
||||
if (config->table) {
|
||||
table_bytes = sizeof(*config->table) * config->table_size;
|
||||
mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL);
|
||||
mix->table = kmemdup_array(config->table, config->table_size,
|
||||
sizeof(*mix->table), GFP_KERNEL);
|
||||
if (!mix->table)
|
||||
goto free_mix;
|
||||
|
||||
|
|
@ -470,9 +469,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
|
|||
}
|
||||
|
||||
if (config->mux_table) {
|
||||
table_bytes = sizeof(u32) * num_parents;
|
||||
mix->mux_table = kmemdup(config->mux_table, table_bytes,
|
||||
GFP_KERNEL);
|
||||
mix->mux_table = kmemdup_array(config->mux_table, num_parents,
|
||||
sizeof(*mix->mux_table), GFP_KERNEL);
|
||||
if (!mix->mux_table) {
|
||||
kfree(mix->table);
|
||||
goto free_mix;
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
|||
for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
if (of_find_property(np, "clock-indices", &i))
|
||||
if (of_property_present(np, "clock-indices"))
|
||||
idxname = "clock-indices";
|
||||
else
|
||||
idxname = "renesas,clock-indices";
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
|
|||
|
||||
/* enable power domain and clocks */
|
||||
pm_runtime_enable(priv->dev);
|
||||
ret = pm_runtime_get_sync(priv->dev);
|
||||
ret = pm_runtime_resume_and_get(priv->dev);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -240,6 +240,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to get atl clock %d from provider\n",
|
||||
__func__, i);
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ static void __init clk_sp810_of_setup(struct device_node *node)
|
|||
init.parent_names = parent_names;
|
||||
init.num_parents = num;
|
||||
|
||||
deprecated = !of_find_property(node, "assigned-clock-parents", NULL);
|
||||
deprecated = !of_property_present(node, "assigned-clock-parents");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sp810->timerclken); i++) {
|
||||
snprintf(name, sizeof(name), "sp810_%d_%d", instance, i);
|
||||
|
|
|
|||
|
|
@ -262,9 +262,9 @@ static struct clk_hw *visconti_register_pll(struct visconti_pll_provider *ctx,
|
|||
for (len = 0; rate_table[len].rate != 0; )
|
||||
len++;
|
||||
pll->rate_count = len;
|
||||
pll->rate_table = kmemdup(rate_table,
|
||||
pll->rate_count * sizeof(struct visconti_pll_rate_table),
|
||||
GFP_KERNEL);
|
||||
pll->rate_table = kmemdup_array(rate_table,
|
||||
pll->rate_count, sizeof(*pll->rate_table),
|
||||
GFP_KERNEL);
|
||||
WARN(!pll->rate_table, "%s: could not allocate rate table for %s\n", __func__, name);
|
||||
|
||||
init.ops = &visconti_pll_ops;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user