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net: lan743x: Add support for Clause-45 MDIO PHY management
Add support for Clause-45 MDIO PHY management Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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a2ab95a313
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@ -18,6 +18,11 @@
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#include "lan743x_main.h"
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#include "lan743x_ethtool.h"
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#define MMD_ACCESS_ADDRESS 0
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#define MMD_ACCESS_WRITE 1
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#define MMD_ACCESS_READ 2
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#define MMD_ACCESS_READ_INC 3
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static void pci11x1x_strap_get_status(struct lan743x_adapter *adapter)
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{
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u32 chip_rev;
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@ -814,6 +819,96 @@ static int lan743x_mdiobus_write(struct mii_bus *bus,
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return ret;
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}
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static u32 lan743x_mac_mmd_access(int id, int index, int op)
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{
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u16 dev_addr;
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u32 ret;
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dev_addr = (index >> 16) & 0x1f;
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ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) &
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MAC_MII_ACC_PHY_ADDR_MASK_;
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ret |= (dev_addr << MAC_MII_ACC_MIIMMD_SHIFT_) &
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MAC_MII_ACC_MIIMMD_MASK_;
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if (op == MMD_ACCESS_WRITE)
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ret |= MAC_MII_ACC_MIICMD_WRITE_;
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else if (op == MMD_ACCESS_READ)
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ret |= MAC_MII_ACC_MIICMD_READ_;
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else if (op == MMD_ACCESS_READ_INC)
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ret |= MAC_MII_ACC_MIICMD_READ_INC_;
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else
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ret |= MAC_MII_ACC_MIICMD_ADDR_;
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ret |= (MAC_MII_ACC_MII_BUSY_ | MAC_MII_ACC_MIICL45_);
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return ret;
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}
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static int lan743x_mdiobus_c45_read(struct mii_bus *bus, int phy_id, int index)
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{
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struct lan743x_adapter *adapter = bus->priv;
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u32 mmd_access;
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int ret;
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/* comfirm MII not busy */
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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if (ret < 0)
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return ret;
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if (index & MII_ADDR_C45) {
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/* Load Register Address */
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lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff));
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mmd_access = lan743x_mac_mmd_access(phy_id, index,
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MMD_ACCESS_ADDRESS);
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lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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if (ret < 0)
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return ret;
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/* Read Data */
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mmd_access = lan743x_mac_mmd_access(phy_id, index,
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MMD_ACCESS_READ);
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lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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if (ret < 0)
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return ret;
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ret = lan743x_csr_read(adapter, MAC_MII_DATA);
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return (int)(ret & 0xFFFF);
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}
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ret = lan743x_mdiobus_read(bus, phy_id, index);
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return ret;
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}
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static int lan743x_mdiobus_c45_write(struct mii_bus *bus,
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int phy_id, int index, u16 regval)
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{
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struct lan743x_adapter *adapter = bus->priv;
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u32 mmd_access;
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int ret;
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/* confirm MII not busy */
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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if (ret < 0)
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return ret;
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if (index & MII_ADDR_C45) {
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/* Load Register Address */
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lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff));
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mmd_access = lan743x_mac_mmd_access(phy_id, index,
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MMD_ACCESS_ADDRESS);
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lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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if (ret < 0)
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return ret;
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/* Write Data */
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lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval);
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mmd_access = lan743x_mac_mmd_access(phy_id, index,
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MMD_ACCESS_WRITE);
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lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
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ret = lan743x_mac_mii_wait_till_not_busy(adapter);
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} else {
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ret = lan743x_mdiobus_write(bus, phy_id, index, regval);
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}
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return ret;
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}
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static void lan743x_mac_set_address(struct lan743x_adapter *adapter,
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u8 *addr)
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{
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@ -2847,11 +2942,19 @@ static int lan743x_mdiobus_init(struct lan743x_adapter *adapter)
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netif_dbg(adapter, drv, adapter->netdev,
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"(R)GMII operation\n");
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}
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adapter->mdiobus->probe_capabilities = MDIOBUS_C22_C45;
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adapter->mdiobus->read = lan743x_mdiobus_c45_read;
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adapter->mdiobus->write = lan743x_mdiobus_c45_write;
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adapter->mdiobus->name = "lan743x-mdiobus-c45";
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netif_dbg(adapter, drv, adapter->netdev, "lan743x-mdiobus-c45\n");
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} else {
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adapter->mdiobus->read = lan743x_mdiobus_read;
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adapter->mdiobus->write = lan743x_mdiobus_write;
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adapter->mdiobus->name = "lan743x-mdiobus";
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netif_dbg(adapter, drv, adapter->netdev, "lan743x-mdiobus\n");
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}
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adapter->mdiobus->read = lan743x_mdiobus_read;
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adapter->mdiobus->write = lan743x_mdiobus_write;
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adapter->mdiobus->name = "lan743x-mdiobus";
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snprintf(adapter->mdiobus->id, MII_BUS_ID_SIZE,
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"pci-%s", pci_name(adapter->pdev));
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@ -151,6 +151,13 @@
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#define MAC_RX_ADDRL (0x11C)
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#define MAC_MII_ACC (0x120)
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#define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16)
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#define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
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#define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
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#define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1)
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#define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)
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#define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3)
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#define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4)
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#define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11)
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#define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
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#define MAC_MII_ACC_MIIRINDA_SHIFT_ (6)
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@ -159,6 +166,15 @@
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#define MAC_MII_ACC_MII_WRITE_ (0x00000002)
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#define MAC_MII_ACC_MII_BUSY_ BIT(0)
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#define MAC_MII_ACC_MIIMMD_SHIFT_ (6)
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#define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
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#define MAC_MII_ACC_MIICL45_ BIT(3)
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#define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
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#define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
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#define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
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#define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
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#define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
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#define MAC_MII_DATA (0x124)
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#define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
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