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arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells

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Add missing address-cells 0 to the PCI interrupt node to silence W=1
warning:

  uniphier-pxs3.dtsi:915.4-918.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map:
    Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback

Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
   the fourth component "parent unit address", which size is defined by
   '#address-cells' of the node pointed to by the interrupt-parent
   component, is not used (=0)

Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20250822133318.312232-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Krzysztof Kozlowski 2025-08-22 15:33:20 +02:00
parent 613fb0c8bd
commit a29bf0b10a
1 changed files with 1 additions and 0 deletions
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arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
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@ -921,6 +921,7 @@ pcie: pcie@66000000 {
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;