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drm/xe/reg_sr: Simplify check for masked registers

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For all RTP actions, clr_bits is a superset of the bits being modified.
That's also why the check for "changing all bits" can be done with
`clr_bits + 1`. So always use clr_bits for setting the upper bits of a
masked register.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://lore.kernel.org/r/20230906012053.1733755-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Lucas De Marchi 2023-09-05 18:20:50 -07:00 committed by Rodrigo Vivi
parent 8bc454baf4
commit a2112949e5
2 changed files with 8 additions and 5 deletions
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8
drivers/gpu/drm/xe/xe_reg_sr.c
View File

@ -153,15 +153,15 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
u32 val;
/*
* If this is a masked register, need to figure what goes on the upper
* 16 bits: it's either the clr_bits (when using FIELD_SET and WR) or
* the set_bits, when using SET.
* If this is a masked register, need to set the upper 16 bits.
* Set them to clr_bits since that is always a superset of the bits
* being modified.
*
* When it's not masked, we have to read it from hardware, unless we are
* supposed to set all bits.
*/
if (reg.masked)
val = (entry->clr_bits ?: entry->set_bits) << 16;
val = entry->clr_bits << 16;
else if (entry->clr_bits + 1)
val = (reg.mcr ?
xe_gt_mcr_unicast_read_any(gt, reg_mcr) :

5
drivers/gpu/drm/xe/xe_rtp_types.h
View File

@ -22,7 +22,10 @@ struct xe_gt;
struct xe_rtp_action {
/** @reg: Register */
struct xe_reg reg;
/** @clr_bits: bits to clear when updating register */
/**
* @clr_bits: bits to clear when updating register. It's always a
* superset of bits being modified
*/
u32 clr_bits;
/** @set_bits: bits to set when updating register */
u32 set_bits;