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A runtime_pm guard for page-fault worker and a cache flush fix.

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Merge tag 'drm-xe-fixes-2026-09-10' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes

A runtime_pm guard for page-fault worker and a cache flush fix.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/aqLD4xjzFF6ROxBu@intel.com
This commit is contained in:
Dave Airlie 2026-09-11 16:13:23 +10:00
commit a202936da8
4 changed files with 25 additions and 0 deletions
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1
drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
View File

@ -46,6 +46,7 @@
#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
#define PIPE_CONTROL0_QUEUE_DRAIN_MODE BIT(12)
#define PIPE_CONTROL0_UNTYPED_DATAPORT_CACHE_FLUSH BIT(11) /* gen12 */
#define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */

10
drivers/gpu/drm/xe/xe_pagefault.c
View File

@ -16,6 +16,7 @@
#include "xe_hw_engine.h"
#include "xe_pagefault.h"
#include "xe_pagefault_types.h"
#include "xe_pm.h"
#include "xe_svm.h"
#include "xe_trace_bo.h"
#include "xe_vm.h"
@ -292,9 +293,17 @@ static void xe_pagefault_queue_work(struct work_struct *w)
{
struct xe_pagefault_queue *pf_queue =
container_of(w, typeof(*pf_queue), worker);
struct xe_device *xe = pf_queue->xe;
struct xe_pagefault pf;
unsigned long threshold;
/*
* A live VM holds a PM reference, but a torn-down VM does not.
* Guard the entire worker loop to safely drain stale faults and
* prevent autosuspends from desyncing batched CT flushes.
*/
guard(xe_pm_runtime)(xe);
#define USM_QUEUE_MAX_RUNTIME_MS 20
threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS);
@ -365,6 +374,7 @@ static int xe_pagefault_queue_init(struct xe_device *xe,
drm_dbg(&xe->drm, "xe_pagefault_entry_size=%d, total_num_eus=%d, pf_queue->size=%u",
xe_pagefault_entry_size(), total_num_eus, pf_queue->size);
pf_queue->xe = xe;
spin_lock_init(&pf_queue->lock);
INIT_WORK(&pf_queue->worker, xe_pagefault_queue_work);

3
drivers/gpu/drm/xe/xe_pagefault_types.h
View File

@ -8,6 +8,7 @@
#include <linux/workqueue.h>
struct xe_device;
struct xe_gt;
struct xe_pagefault;
@ -118,6 +119,8 @@ struct xe_pagefault {
* queue to absorb the device’s worst-case number of outstanding faults.
*/
struct xe_pagefault_queue {
/** @xe: Back-pointer to the Xe device */
struct xe_device *xe;
/**
* @data: Data in queue containing struct xe_pagefault, protected by
* @lock

11
drivers/gpu/drm/xe/xe_ring_ops.c
View File

@ -212,6 +212,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
{
struct xe_exec_queue *q = job->q;
struct xe_gt *gt = q->gt;
struct xe_device *xe = gt_to_xe(gt);
bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
u32 flags0, flags1;
@ -220,6 +221,16 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
flags0 = PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
/*
* Prior to MTL, HDC Pipeline Flush reliably also flushes the LSC
* untyped L1 dataport cache, provided HDC_CHICKEN0 is programmed
* correctly. Starting with MTL that coupling no longer holds
* regardless of how HDC_CHICKEN0 is programmed, but explicitly
* requesting the flush via PIPE_CONTROL is itself only reliable
* from Xe2 onward, so only gate it in on Xe2+.
*/
if (GRAPHICS_VERx100(xe) >= 2000)
flags0 |= PIPE_CONTROL0_UNTYPED_DATAPORT_CACHE_FLUSH;
flags1 = (PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |