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irqchip/gic-v5: Defer default SPI and LPI IAFFID programming

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SPI and LPI interrupts do not have an architected default value for their
IAFFID (interrupt affinity ID) - the property that determines an IRQ
affinity.

Current code awkwardly tries to set a default IAFFID value corresponding
to the logical cpu executing the gicv5_hwirq_init() function at SPI/LPI
allocation time.

There are two issues with this approach:

- gicv5_hwirq_init() is called in preemptible context and current code
  uses smp_processor_id() to check the logical cpu executing the function.
  Whilst that's harmless, it can spit a splat on DEBUG_PREEMPT kernels
- Setting the default SPI/LPI IAFFID to the one belonging to the cpu
  executing the IRQ allocation is a completely arbitrary choice

It is saner to remove the SPI/LPI IAFFID set-up in the SPI/LPI domain IRQ
allocation code and flag SPI/LPI irqchips as IRQCHIP_AFFINITY_PRE_STARTUP
so that the SPI/LPI affinity is initialized by IRQ core to a sane value
before an IRQ is started up using the respective irq_chip
irq_set_affinity() callback.

Fixes: 5cb1b6dab2 ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
Fixes: 0f01013258 ("irqchip/gic-v5: Add GICv5 LPI/IPI support")
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260812-gicv5-7-2-fixes-v1-7-3743e82c69a4@kernel.org
This commit is contained in:
Lorenzo Pieralisi 2026-08-12 11:10:35 +02:00 committed by Thomas Gleixner
parent 9dfcc21872
commit a1ee1a1ca7
1 changed files with 4 additions and 14 deletions
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18
drivers/irqchip/irq-gic-v5.c
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@ -87,25 +87,13 @@ static void gicv5_ppi_priority_init(void)
static void gicv5_hwirq_init(irq_hw_number_t hwirq, u8 priority, u8 hwirq_type)
{
u64 cdpri, cdaff;
u16 iaffid;
int ret;
u64 cdpri;
if (hwirq_type == GICV5_HWIRQ_TYPE_LPI || hwirq_type == GICV5_HWIRQ_TYPE_SPI) {
cdpri = FIELD_PREP(GICV5_GIC_CDPRI_PRIORITY_MASK, priority) |
FIELD_PREP(GICV5_GIC_CDPRI_TYPE_MASK, hwirq_type) |
FIELD_PREP(GICV5_GIC_CDPRI_ID_MASK, hwirq);
gic_insn(cdpri, CDPRI);
ret = gicv5_irs_cpu_to_iaffid(smp_processor_id(), &iaffid);
if (WARN_ON_ONCE(ret))
return;
cdaff = FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) |
FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) |
FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, hwirq);
gic_insn(cdaff, CDAFF);
}
}
@ -548,6 +536,7 @@ static const struct irq_chip gicv5_spi_irq_chip = {
.irq_get_irqchip_state = gicv5_spi_irq_get_irqchip_state,
.irq_set_irqchip_state = gicv5_spi_irq_set_irqchip_state,
.flags = IRQCHIP_SET_TYPE_MASKED |
IRQCHIP_AFFINITY_PRE_STARTUP |
IRQCHIP_SKIP_SET_WAKE |
IRQCHIP_MASK_ON_SUSPEND,
};
@ -561,7 +550,8 @@ static const struct irq_chip gicv5_lpi_irq_chip = {
.irq_retrigger = gicv5_lpi_irq_retrigger,
.irq_get_irqchip_state = gicv5_lpi_irq_get_irqchip_state,
.irq_set_irqchip_state = gicv5_lpi_irq_set_irqchip_state,
.flags = IRQCHIP_SKIP_SET_WAKE |
.flags = IRQCHIP_AFFINITY_PRE_STARTUP |
IRQCHIP_SKIP_SET_WAKE |
IRQCHIP_MASK_ON_SUSPEND,
};