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arm64: dts: s32g: add PWM support for s32g2 and s32g3

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Add PWM0 and PWM1 for S32G2 and S32G3 SoCs

Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Khristine Andreea Barbulescu 2026-06-02 12:23:51 +02:00 committed by Frank Li
parent 65210e81f7
commit a1b81a560e
3 changed files with 131 additions and 1 deletions
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26
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@ -563,6 +563,19 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
pwm0: pwm@401f4000 {
compatible = "nxp,s32g2-ftm-pwm";
reg = <0x401f4000 0x1000>;
#pwm-cells = <3>;
clocks = <&clks 5>,
<&clks 6>,
<&clks 5>,
<&clks 5>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
status = "disabled";
};
adc0: adc@401f8000 {
compatible = "nxp,s32g2-sar-adc";
reg = <0x401f8000 0x1000>;
@ -745,6 +758,19 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
pwm1: pwm@402e4000 {
compatible = "nxp,s32g2-ftm-pwm";
reg = <0x402e4000 0x1000>;
#pwm-cells = <3>;
clocks = <&clks 7>,
<&clks 8>,
<&clks 7>,
<&clks 7>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
status = "disabled";
};
adc1: adc@402e8000 {
compatible = "nxp,s32g2-sar-adc";
reg = <0x402e8000 0x1000>;

28
arch/arm64/boot/dts/freescale/s32g3.dtsi
View File

@ -626,6 +626,20 @@ i2c2: i2c@401ec000 {
status = "disabled";
};
pwm0: pwm@401f4000 {
compatible = "nxp,s32g3-ftm-pwm",
"nxp,s32g2-ftm-pwm";
reg = <0x401f4000 0x1000>;
#pwm-cells = <3>;
clocks = <&clks 5>,
<&clks 6>,
<&clks 5>,
<&clks 5>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
status = "disabled";
};
adc0: adc@401f8000 {
compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
reg = <0x401f8000 0x1000>;
@ -820,6 +834,20 @@ i2c4: i2c@402dc000 {
status = "disabled";
};
pwm1: pwm@402e4000 {
compatible = "nxp,s32g3-ftm-pwm",
"nxp,s32g2-ftm-pwm";
reg = <0x402e4000 0x1000>;
#pwm-cells = <3>;
clocks = <&clks 7>,
<&clks 8>,
<&clks 7>,
<&clks 7>;
clock-names = "ftm_sys", "ftm_ext",
"ftm_fix", "ftm_cnt_clk_en";
status = "disabled";
};
adc1: adc@402e8000 {
compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
reg = <0x402e8000 0x1000>;

78
arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2024 NXP
* Copyright 2024, 2026 NXP
*
* Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
* Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
@ -245,6 +245,70 @@ dspi5-grp4 {
bias-pull-up;
};
};
ftm0_pins: ftm0-pins {
ftm0-grp0 {
pinmux = <0x2912>;
};
ftm0-grp1 {
pinmux = <0x122>,
<0xb42>;
output-enable;
input-enable;
};
ftm0-grp2 {
pinmux = <0xb13>,
<0xb53>;
output-enable;
input-enable;
};
ftm0-grp3 {
pinmux = <0x2904>;
};
ftm0-grp4 {
pinmux = <0x2925>;
};
ftm0-grp5 {
pinmux = <0x2936>;
};
};
ftm1_pins: ftm1-pins {
ftm1-grp0 {
pinmux = <0x1d3>;
output-enable;
input-enable;
};
ftm1-grp1 {
pinmux = <0x29b4>;
};
ftm1-grp2 {
pinmux = <0x29c3>;
};
ftm1-grp3 {
pinmux = <0x1f4>;
output-enable;
input-enable;
};
ftm1-grp4 {
pinmux = <0x202>;
output-enable;
input-enable;
};
ftm1-grp5 {
pinmux = <0x29d2>;
};
};
};
&can0 {
@ -293,6 +357,18 @@ &i2c4 {
status = "okay";
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&ftm0_pins>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&ftm1_pins>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&dspi1_pins>;
pinctrl-names = "default";