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arm64: dts: rockchip: Enable USB 3.0 ports on orangepi-5-plus

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The Orange Pi 5 Plus has its first USB 3.0 interface on the SoC wired
directly to the USB type C port next to the MASKROM button, and the
second interface wired to a USB 3.0 hub which in turn is connected to
the USB 3.0 host ports on the board, as well as the USB 2.0 connection
on the M.2 E-key slot.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Ondrej Jirman <megi@xff.cz>
Link: https://lore.kernel.org/r/20241220161240.109253-1-wens@kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Chen-Yu Tsai 2024-12-21 00:12:40 +08:00 committed by Heiko Stuebner
parent b53864811b
commit a15d12f36e
1 changed files with 133 additions and 0 deletions
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133
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
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@ -177,6 +177,18 @@ daicodec: simple-audio-card,codec {
};
};
vbus5v0_typec: regulator-vbus-typec {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
regulator-name = "vbus5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
compatible = "regulator-fixed";
enable-active-high;
@ -344,6 +356,57 @@ &i2c6 {
clock-frequency = <400000>;
status = "okay";
usbc0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
status = "okay";
usb_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
power-role = "dual";
op-sink-microwatt = <10>;
source-pdos = <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 10, PDO_FIXED_USB_COMM)>;
try-power-role = "source";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_hs: endpoint {
remote-endpoint = <&usb_host0_xhci_drd_sw>;
};
};
port@1 {
reg = <1>;
usbc0_ss: endpoint {
remote-endpoint = <&usbdp_phy0_typec_ss>;
};
};
port@2 {
reg = <2>;
usbc0_sbu: endpoint {
remote-endpoint = <&usbdp_phy0_typec_sbu>;
};
};
};
};
};
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
@ -485,6 +548,16 @@ vcc5v0_usb20_en: vcc5v0-usb20-en {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm2 {
@ -876,6 +949,23 @@ &tsadc {
status = "okay";
};
&u2phy0 {
status = "okay";
};
&u2phy0_otg {
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_otg {
phy-supply = <&vcc5v0_sys>;
status = "okay";
};
&u2phy2 {
status = "okay";
};
@ -904,6 +994,33 @@ &uart9 {
status = "okay";
};
&usbdp_phy0 {
mode-switch;
orientation-switch;
sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_typec_ss: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_ss>;
};
usbdp_phy0_typec_sbu: endpoint@1 {
reg = <1>;
remote-endpoint = <&usbc0_sbu>;
};
};
};
&usbdp_phy1 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
@ -912,6 +1029,17 @@ &usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
usb-role-switch;
status = "okay";
port {
usb_host0_xhci_drd_sw: endpoint {
remote-endpoint = <&usbc0_hs>;
};
};
};
&usb_host1_ehci {
status = "okay";
};
@ -920,6 +1048,11 @@ &usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
dr_mode = "host";
status = "okay";
};
&vop_mmu {
status = "okay";
};