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synced 2026-05-28 17:13:52 +02:00
drm/i915/gmch: split out soc/intel_gmch
The GMCH related code is a bit too low level and out of place for the high level i915_driver.c file. Split out to a separate file under soc/. Rename the functions accordingly. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/980a5e08b397bc0dbccf93cd84798772233ce75c.1673958757.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula
parent
9bd5de4abd
commit
a13144e228
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@ -63,6 +63,7 @@ i915-y += i915_driver.o \
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# core peripheral code
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i915-y += \
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soc/intel_dram.o \
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soc/intel_gmch.o \
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soc/intel_pch.o
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# core library code
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@ -34,7 +34,6 @@
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/pnp.h>
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#include <linux/slab.h>
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#include <linux/string_helpers.h>
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#include <linux/vga_switcheroo.h>
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@ -78,6 +77,7 @@
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#include "pxp/intel_pxp_pm.h"
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#include "soc/intel_dram.h"
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#include "soc/intel_gmch.h"
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#include "i915_file_private.h"
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#include "i915_debugfs.h"
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@ -107,141 +107,6 @@
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static const struct drm_driver i915_drm_driver;
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static void i915_release_bridge_dev(struct drm_device *dev,
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void *bridge)
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{
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pci_dev_put(bridge);
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}
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static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
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{
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int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
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dev_priv->gmch.pdev =
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pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
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if (!dev_priv->gmch.pdev) {
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drm_err(&dev_priv->drm, "bridge device not found\n");
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return -EIO;
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}
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return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev,
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dev_priv->gmch.pdev);
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}
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/* Allocate space for the MCH regs if needed, return nonzero on error */
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static int
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intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
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{
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int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp_lo, temp_hi = 0;
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u64 mchbar_addr;
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int ret;
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if (GRAPHICS_VER(dev_priv) >= 4)
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pci_read_config_dword(dev_priv->gmch.pdev, reg + 4, &temp_hi);
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pci_read_config_dword(dev_priv->gmch.pdev, reg, &temp_lo);
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mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
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/* If ACPI doesn't have it, assume we need to allocate it ourselves */
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#ifdef CONFIG_PNP
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if (mchbar_addr &&
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pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
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return 0;
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#endif
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/* Get some space for it */
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dev_priv->gmch.mch_res.name = "i915 MCHBAR";
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dev_priv->gmch.mch_res.flags = IORESOURCE_MEM;
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ret = pci_bus_alloc_resource(dev_priv->gmch.pdev->bus,
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&dev_priv->gmch.mch_res,
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MCHBAR_SIZE, MCHBAR_SIZE,
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PCIBIOS_MIN_MEM,
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0, pcibios_align_resource,
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dev_priv->gmch.pdev);
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if (ret) {
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drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
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dev_priv->gmch.mch_res.start = 0;
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return ret;
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}
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if (GRAPHICS_VER(dev_priv) >= 4)
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pci_write_config_dword(dev_priv->gmch.pdev, reg + 4,
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upper_32_bits(dev_priv->gmch.mch_res.start));
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pci_write_config_dword(dev_priv->gmch.pdev, reg,
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lower_32_bits(dev_priv->gmch.mch_res.start));
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return 0;
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}
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/* Setup MCHBAR if possible, return true if we should disable it again */
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static void
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intel_setup_mchbar(struct drm_i915_private *dev_priv)
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{
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int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp;
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bool enabled;
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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return;
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dev_priv->gmch.mchbar_need_disable = false;
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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pci_read_config_dword(dev_priv->gmch.pdev, DEVEN, &temp);
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enabled = !!(temp & DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
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enabled = temp & 1;
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}
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/* If it's already enabled, don't have to do anything */
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if (enabled)
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return;
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if (intel_alloc_mchbar_resource(dev_priv))
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return;
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dev_priv->gmch.mchbar_need_disable = true;
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/* Space is allocated or reserved, so enable it. */
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
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temp | DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
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pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg, temp | 1);
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}
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}
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static void
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intel_teardown_mchbar(struct drm_i915_private *dev_priv)
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{
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int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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if (dev_priv->gmch.mchbar_need_disable) {
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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u32 deven_val;
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pci_read_config_dword(dev_priv->gmch.pdev, DEVEN,
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&deven_val);
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deven_val &= ~DEVEN_MCHBAR_EN;
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pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
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deven_val);
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} else {
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u32 mchbar_val;
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg,
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&mchbar_val);
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mchbar_val &= ~1;
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pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg,
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mchbar_val);
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}
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}
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if (dev_priv->gmch.mch_res.start)
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release_resource(&dev_priv->gmch.mch_res);
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}
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static int i915_workqueues_init(struct drm_i915_private *dev_priv)
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{
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/*
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@ -447,7 +312,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
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if (i915_inject_probe_failure(dev_priv))
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return -ENODEV;
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ret = i915_get_bridge_dev(dev_priv);
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ret = intel_gmch_bridge_setup(dev_priv);
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if (ret < 0)
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return ret;
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@ -464,7 +329,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
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}
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/* Try to make sure MCHBAR is enabled before poking at it */
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intel_setup_mchbar(dev_priv);
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intel_gmch_bar_setup(dev_priv);
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intel_device_info_runtime_init(dev_priv);
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for_each_gt(gt, dev_priv, i) {
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@ -479,7 +344,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
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return 0;
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err_uncore:
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intel_teardown_mchbar(dev_priv);
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intel_gmch_bar_teardown(dev_priv);
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return ret;
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}
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@ -490,7 +355,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
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*/
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static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
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{
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intel_teardown_mchbar(dev_priv);
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intel_gmch_bar_teardown(dev_priv);
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}
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/**
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145
drivers/gpu/drm/i915/soc/intel_gmch.c
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145
drivers/gpu/drm/i915/soc/intel_gmch.c
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@ -0,0 +1,145 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include <linux/pci.h>
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#include <linux/pnp.h>
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#include <drm/drm_managed.h>
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#include "i915_drv.h"
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#include "intel_gmch.h"
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#include "intel_pci_config.h"
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static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
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{
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pci_dev_put(bridge);
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}
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int intel_gmch_bridge_setup(struct drm_i915_private *dev_priv)
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{
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int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
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dev_priv->gmch.pdev =
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pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
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if (!dev_priv->gmch.pdev) {
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drm_err(&dev_priv->drm, "bridge device not found\n");
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return -EIO;
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}
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return drmm_add_action_or_reset(&dev_priv->drm, intel_gmch_bridge_release,
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dev_priv->gmch.pdev);
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}
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/* Allocate space for the MCH regs if needed, return nonzero on error */
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static int
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intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
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{
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int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp_lo, temp_hi = 0;
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u64 mchbar_addr;
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int ret;
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if (GRAPHICS_VER(dev_priv) >= 4)
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pci_read_config_dword(dev_priv->gmch.pdev, reg + 4, &temp_hi);
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pci_read_config_dword(dev_priv->gmch.pdev, reg, &temp_lo);
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mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
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/* If ACPI doesn't have it, assume we need to allocate it ourselves */
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#ifdef CONFIG_PNP
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if (mchbar_addr &&
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pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
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return 0;
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#endif
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/* Get some space for it */
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dev_priv->gmch.mch_res.name = "i915 MCHBAR";
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dev_priv->gmch.mch_res.flags = IORESOURCE_MEM;
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ret = pci_bus_alloc_resource(dev_priv->gmch.pdev->bus,
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&dev_priv->gmch.mch_res,
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MCHBAR_SIZE, MCHBAR_SIZE,
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PCIBIOS_MIN_MEM,
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0, pcibios_align_resource,
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dev_priv->gmch.pdev);
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if (ret) {
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drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
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dev_priv->gmch.mch_res.start = 0;
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return ret;
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}
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if (GRAPHICS_VER(dev_priv) >= 4)
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pci_write_config_dword(dev_priv->gmch.pdev, reg + 4,
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upper_32_bits(dev_priv->gmch.mch_res.start));
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pci_write_config_dword(dev_priv->gmch.pdev, reg,
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lower_32_bits(dev_priv->gmch.mch_res.start));
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return 0;
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}
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/* Setup MCHBAR if possible, return true if we should disable it again */
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void intel_gmch_bar_setup(struct drm_i915_private *dev_priv)
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{
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int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp;
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bool enabled;
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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return;
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dev_priv->gmch.mchbar_need_disable = false;
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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pci_read_config_dword(dev_priv->gmch.pdev, DEVEN, &temp);
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enabled = !!(temp & DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
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enabled = temp & 1;
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}
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/* If it's already enabled, don't have to do anything */
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if (enabled)
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return;
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if (intel_alloc_mchbar_resource(dev_priv))
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return;
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dev_priv->gmch.mchbar_need_disable = true;
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/* Space is allocated or reserved, so enable it. */
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
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temp | DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg, &temp);
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pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg, temp | 1);
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}
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}
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void intel_gmch_bar_teardown(struct drm_i915_private *dev_priv)
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{
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int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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if (dev_priv->gmch.mchbar_need_disable) {
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if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
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u32 deven_val;
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pci_read_config_dword(dev_priv->gmch.pdev, DEVEN,
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&deven_val);
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deven_val &= ~DEVEN_MCHBAR_EN;
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pci_write_config_dword(dev_priv->gmch.pdev, DEVEN,
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deven_val);
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} else {
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u32 mchbar_val;
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pci_read_config_dword(dev_priv->gmch.pdev, mchbar_reg,
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&mchbar_val);
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mchbar_val &= ~1;
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pci_write_config_dword(dev_priv->gmch.pdev, mchbar_reg,
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mchbar_val);
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}
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}
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if (dev_priv->gmch.mch_res.start)
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release_resource(&dev_priv->gmch.mch_res);
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}
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15
drivers/gpu/drm/i915/soc/intel_gmch.h
Normal file
15
drivers/gpu/drm/i915/soc/intel_gmch.h
Normal file
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_GMCH_H__
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#define __INTEL_GMCH_H__
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struct drm_i915_private;
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int intel_gmch_bridge_setup(struct drm_i915_private *i915);
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void intel_gmch_bar_setup(struct drm_i915_private *i915);
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void intel_gmch_bar_teardown(struct drm_i915_private *i915);
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#endif /* __INTEL_GMCH_H__ */
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