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drm/i915/psr: Add new define for PSR idle timeout

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Currently we are using value 50ms as timeout for waiting PSR to idle. Add
own define for this purpose.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250905072708.2659411-3-jouni.hogander@intel.com
This commit is contained in:
Jouni Högander 2025-09-05 10:27:06 +03:00
parent 485aaebd73
commit a0f7f3b165
1 changed files with 12 additions and 8 deletions
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20
drivers/gpu/drm/i915/display/intel_psr.c
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@ -2997,6 +2997,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
}
}
/*
* From bspec: Panel Self Refresh (BDW+)
* Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
#define PSR_IDLE_TIMEOUT_MS 50
static int
_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state)
{
@ -3010,7 +3018,8 @@ _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
*/
return intel_de_wait_for_clear(display,
EDP_PSR2_STATUS(display, cpu_transcoder),
EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
PSR_IDLE_TIMEOUT_MS);
}
static int
@ -3019,15 +3028,10 @@ _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state
struct intel_display *display = to_intel_display(new_crtc_state);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
/*
* From bspec: Panel Self Refresh (BDW+)
* Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
return intel_de_wait_for_clear(display,
psr_status_reg(display, cpu_transcoder),
EDP_PSR_STATUS_STATE_MASK, 50);
EDP_PSR_STATUS_STATE_MASK,
PSR_IDLE_TIMEOUT_MS);
}
/**