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drm/amd/display: Fix DCN42 gpuvm_min_page_size_kbytes in SOC BB

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[Why & How]
To match the HW specification this should be 4, not 256.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas 2026-03-19 14:39:14 -04:00 committed by Alex Deucher
parent 07ac59230d
commit a0ce0de0ce
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h
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@ -208,7 +208,7 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = {
.fabric_datapath_to_dcn_data_return_bytes = 32,
.return_bus_width_bytes = 64,
.hostvm_min_page_size_kbytes = 4,
.gpuvm_min_page_size_kbytes = 256,
.gpuvm_min_page_size_kbytes = 4,
.gpuvm_max_page_table_levels = 1,
.hostvm_max_non_cached_page_table_levels = 2,
.phy_downspread_percent = 0.38,