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hinic3: HW capability initialization
Use mailbox to get device capability for initializing driver capability. Co-developed-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Zhu Yikai <zhuyikai1@h-partners.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Link: https://patch.msgid.link/8f4cbd99306a14cee1b7621714c269a02a5082dc.1757653621.git.zhuyikai1@h-partners.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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@ -8,6 +8,67 @@
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#include "hinic3_hwif.h"
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#include "hinic3_mbox.h"
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#define HINIC3_CFG_MAX_QP 256
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static void hinic3_parse_pub_res_cap(struct hinic3_hwdev *hwdev,
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struct hinic3_dev_cap *cap,
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const struct cfg_cmd_dev_cap *dev_cap,
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enum hinic3_func_type type)
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{
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cap->port_id = dev_cap->port_id;
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cap->supp_svcs_bitmap = dev_cap->svc_cap_en;
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}
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static void hinic3_parse_l2nic_res_cap(struct hinic3_hwdev *hwdev,
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struct hinic3_dev_cap *cap,
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const struct cfg_cmd_dev_cap *dev_cap,
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enum hinic3_func_type type)
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{
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struct hinic3_nic_service_cap *nic_svc_cap = &cap->nic_svc_cap;
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nic_svc_cap->max_sqs = min(dev_cap->nic_max_sq_id + 1,
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HINIC3_CFG_MAX_QP);
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}
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static void hinic3_parse_dev_cap(struct hinic3_hwdev *hwdev,
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const struct cfg_cmd_dev_cap *dev_cap,
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enum hinic3_func_type type)
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{
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struct hinic3_dev_cap *cap = &hwdev->cfg_mgmt->cap;
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/* Public resource */
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hinic3_parse_pub_res_cap(hwdev, cap, dev_cap, type);
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/* L2 NIC resource */
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if (hinic3_support_nic(hwdev))
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hinic3_parse_l2nic_res_cap(hwdev, cap, dev_cap, type);
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}
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static int get_cap_from_fw(struct hinic3_hwdev *hwdev,
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enum hinic3_func_type type)
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{
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struct mgmt_msg_params msg_params = {};
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struct cfg_cmd_dev_cap dev_cap = {};
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int err;
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dev_cap.func_id = hinic3_global_func_id(hwdev);
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mgmt_msg_params_init_default(&msg_params, &dev_cap, sizeof(dev_cap));
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err = hinic3_send_mbox_to_mgmt(hwdev, MGMT_MOD_CFGM,
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CFG_CMD_GET_DEV_CAP, &msg_params);
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if (err || dev_cap.head.status) {
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dev_err(hwdev->dev,
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"Failed to get capability from FW, err: %d, status: 0x%x\n",
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err, dev_cap.head.status);
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return -EIO;
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}
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hinic3_parse_dev_cap(hwdev, &dev_cap, type);
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return 0;
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}
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static int hinic3_init_irq_info(struct hinic3_hwdev *hwdev)
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{
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struct hinic3_cfg_mgmt_info *cfg_mgmt = hwdev->cfg_mgmt;
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@ -153,6 +214,11 @@ void hinic3_free_irq(struct hinic3_hwdev *hwdev, u32 irq_id)
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mutex_unlock(&irq_info->irq_mutex);
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}
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int hinic3_init_capability(struct hinic3_hwdev *hwdev)
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{
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return get_cap_from_fw(hwdev, HINIC3_FUNC_TYPE_VF);
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}
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bool hinic3_support_nic(struct hinic3_hwdev *hwdev)
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{
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return hwdev->cfg_mgmt->cap.supp_svcs_bitmap &
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@ -49,6 +49,7 @@ int hinic3_alloc_irqs(struct hinic3_hwdev *hwdev, u16 num,
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struct msix_entry *alloc_arr, u16 *act_num);
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void hinic3_free_irq(struct hinic3_hwdev *hwdev, u32 irq_id);
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int hinic3_init_capability(struct hinic3_hwdev *hwdev);
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bool hinic3_support_nic(struct hinic3_hwdev *hwdev);
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u16 hinic3_func_max_qnum(struct hinic3_hwdev *hwdev);
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u8 hinic3_physical_port_id(struct hinic3_hwdev *hwdev);
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@ -51,6 +51,48 @@ static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_para
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msg_params->timeout_ms = 0;
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}
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enum cfg_cmd {
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CFG_CMD_GET_DEV_CAP = 0,
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};
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/* Device capabilities, defined by hw */
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struct cfg_cmd_dev_cap {
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struct mgmt_msg_head head;
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u16 func_id;
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u16 rsvd1;
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/* Public resources */
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u8 host_id;
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u8 ep_id;
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u8 er_id;
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u8 port_id;
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u16 host_total_func;
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u8 host_pf_num;
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u8 pf_id_start;
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u16 host_vf_num;
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u16 vf_id_start;
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u8 host_oq_id_mask_val;
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u8 timer_en;
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u8 host_valid_bitmap;
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u8 rsvd_host;
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u16 svc_cap_en;
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u16 max_vf;
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u8 flexq_en;
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u8 valid_cos_bitmap;
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u8 port_cos_valid_bitmap;
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u8 rsvd2[45];
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/* l2nic */
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u16 nic_max_sq_id;
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u16 nic_max_rq_id;
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u16 nic_default_num_queues;
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u8 rsvd3[250];
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};
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/* COMM Commands between Driver to fw */
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enum comm_cmd {
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/* Commands for clearing FLR and resources */
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@ -479,6 +479,12 @@ int hinic3_init_hwdev(struct pci_dev *pdev)
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goto err_free_cfg_mgmt;
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}
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err = hinic3_init_capability(hwdev);
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if (err) {
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dev_err(hwdev->dev, "Failed to init capability\n");
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goto err_uninit_comm_ch;
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}
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err = hinic3_set_comm_features(hwdev, hwdev->features,
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COMM_MAX_FEATURE_QWORD);
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if (err) {
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