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arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

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Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially improving
SPI throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Fong, Yan Kei 2025-09-11 09:58:12 +08:00 committed by Dinh Nguyen
parent e928e15a3e
commit a025e1fb35
1 changed files with 2 additions and 0 deletions
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2
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
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@ -77,6 +77,8 @@ flash@0 {
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";