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wifi: mt76: mt7925: add MT7928 DMA configuration

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Add MT7928 DMA queue layout, DMASHDL configuration, prefetch ring
setup, and WFDMA interrupt priority initialization. Select the
MT7928-specific layout and GLO_CFG path in mt7925_dma_init().

Signed-off-by: FC Wei <fc.wei@mediatek.com>
Signed-off-by: Xiong <xiong.huang@mediatek.com>
Signed-off-by: Emery Hsin <emery.hsin@mediatek.com>
Link: https://patch.msgid.link/20260612075313.2578154-5-jb.tsai@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Emery Hsin 2026-06-12 15:53:13 +08:00 committed by Felix Fietkau
parent d92d0b0c06
commit a01a222ab4
6 changed files with 233 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/net/wireless/mediatek/mt76/mt7925/mcu.h
View File

@ -175,6 +175,27 @@ enum connac3_mcu_cipher_type {
CONNAC3_CIPHER_GCMP_256 = 12,
};
enum DMASHDL_GROUP_IDX {
DMASHDL_GROUP_0 = 0,
DMASHDL_GROUP_1,
DMASHDL_GROUP_2,
DMASHDL_GROUP_3,
DMASHDL_GROUP_4,
DMASHDL_GROUP_5,
DMASHDL_GROUP_6,
DMASHDL_GROUP_7,
DMASHDL_GROUP_8,
DMASHDL_GROUP_9,
DMASHDL_GROUP_10,
DMASHDL_GROUP_11,
DMASHDL_GROUP_12,
DMASHDL_GROUP_13,
DMASHDL_GROUP_14,
DMASHDL_GROUP_15,
DMASHDL_GROUP_NUM,
DMASHDL_LITE_GROUP_NUM = 64
};
struct mt7925_mcu_scan_chinfo_event {
u8 nr_chan;
u8 alpha2[3];

8
drivers/net/wireless/mediatek/mt76/mt7925/mt7925.h
View File

@ -15,6 +15,7 @@
#define MT7925_RX_RING_SIZE 1536
#define MT7925_RX_MCU_RING_SIZE 512
#define MT7928_RX_MCU_WA_RING_SIZE 512
#define MT7925_EEPROM_SIZE 3584
#define MT7925_TOKEN_SIZE 8192
@ -139,6 +140,13 @@ enum mt7927_rxq_id {
MT7927_RXQ_DATA2 = 7,
};
enum mt7928_rxq_id {
MT7928_RXQ_BAND0,
MT7928_RXQ_BAND1 = 2,
MT7928_RXQ_MCU_WM = 3,
MT7928_RXQ_MCU_WM2 = 1, /* for tx done */
};
enum {
MODE_OPEN = 0,
MODE_SHARED = 1,

91
drivers/net/wireless/mediatek/mt76/mt7925/pci.c
View File

@ -252,6 +252,27 @@ static const struct mt792x_dma_layout mt7927_dma_layout = {
MT_RX_DATA_RING_BASE),
};
static const struct mt792x_dma_layout mt7928_dma_layout = {
.tx_data0 = mt792x_dma_ring(MT7925_TXQ_BAND0,
MT7925_TX_RING_SIZE,
MT_TX_RING_BASE),
.tx_mcu = mt792x_dma_ring(MT7925_TXQ_MCU_WM,
MT7925_TX_MCU_RING_SIZE,
MT_TX_RING_BASE),
.tx_fwdl = mt792x_dma_ring(MT7925_TXQ_FWDL,
MT7925_TX_FWDL_RING_SIZE,
MT_TX_RING_BASE),
.tx_done = mt792x_dma_ring(MT7928_RXQ_MCU_WM2,
MT7928_RX_MCU_WA_RING_SIZE,
MT_RX_EVENT_RING_BASE),
.rx_mcu = mt792x_dma_ring(MT7928_RXQ_MCU_WM,
MT7925_RX_MCU_RING_SIZE,
MT_RX_EVENT_RING_BASE),
.rx_data = mt792x_dma_ring(MT7928_RXQ_BAND0,
MT7925_RX_RING_SIZE,
MT_RX_DATA_RING_BASE),
};
static int mt7927_dma_init(struct mt792x_dev *dev)
{
int ret;
@ -279,11 +300,62 @@ static int mt7927_dma_init(struct mt792x_dev *dev)
return mt792x_dma_enable(dev);
}
static void mt7928_dma_shdl_lite_init(struct mt792x_dev *dev)
{
u32 addr, idx, grp1_5_quota, grp15_quota;
u32 q2group[8] = {
0x04000000, /* AC00->G0,..., AC03->G4 */
0x04010101, /* AC10->G1,..., AC13->G4 */
0x04020202, /* AC20->G2,..., AC23->G4 */
0x04030303, /* AC30->G3,..., AC33->G4 */
0x00000005, /* ALTX->G5,BMC->G0,BCN->G0 */
0x00000005, /* TGID=1 ALTX->G5 */
0x00000000, /* NAF/NBCN/FIXFID -> G0 */
0x00000005, /* TGID=2 ALTX->G5 */
};
/* RST */
mt76_wr(dev, MT_DMASHDL_LITE_MAIN_CONTROL, MT_DMASHDL_LITE_MAIN_CONTROL_SW_RST);
/* pse page size 0x10, ple page size 0x7e0 */
mt76_wr(dev, MT_DMASHDL_LITE_PAGE_SIZE,
FIELD_PREP(MT_DMASHDL_LITE_PSE_PAGE_SIZE_MASK, 0x10) |
FIELD_PREP(MT_DMASHDL_LITE_PLE_PAGE_SIZE_MASK, 0x7e0));
/* pse max page 8, ple max page 1 */
mt76_wr(dev, MT_DMASHDL_LITE_PKT_MAX_SIZE,
FIELD_PREP(MT_DMASHDL_LITE_PSE_PKT_MAX_SIZE_MASK, 8) |
FIELD_PREP(MT_DMASHDL_LITE_PLE_PKT_MAX_SIZE_MASK, 1));
/* SN/UDF check */
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_SN_CHK0, 0xffffffff);
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_SN_CHK1, 0xffffffff);
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_UDF_CHK0, 0xffffffff);
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_UDF_CHK1, 0xffffffff);
/* q mapping */
for (addr = MT_DMASHDL_LITE_Q_MAPPING0, idx = 0;
idx < ARRAY_SIZE(q2group);
idx++, addr += 4)
mt76_wr(dev, addr, q2group[idx]);
/* refill, set 0 to enable group 0,1,2,3,4,5 & 15 */
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_DISABLE0, 0xffff7fc0);
mt76_wr(dev, MT_DMASHDL_LITE_GROUP_DISABLE1, 0xffffffff);
/* max/min quota */
grp1_5_quota = FIELD_PREP(MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK, 0x3f0) |
FIELD_PREP(MT_DMASHDL_LITE_GROUP_MIN_QUOTA_MASK, 0x10);
grp15_quota = FIELD_PREP(MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK, 0x30);
for (addr = MT_DMASHDL_LITE_GROUP0_QUOTA, idx = 0;
idx < DMASHDL_LITE_GROUP_NUM;
idx++, addr += 4)
mt76_wr(dev, addr, (idx <= 5) ? grp1_5_quota :
((idx == 15) ? grp15_quota : 0));
}
static int mt7925_dma_init(struct mt792x_dev *dev)
{
int ret;
const struct mt792x_dma_layout *layout =
is_mt7928(&dev->mt76) ? &mt7928_dma_layout : &mt7925_dma_layout;
ret = mt792x_dma_alloc_queues(dev, &mt7925_dma_layout);
ret = mt792x_dma_alloc_queues(dev, layout);
if (ret)
return ret;
@ -291,6 +363,9 @@ static int mt7925_dma_init(struct mt792x_dev *dev)
if (ret < 0)
return ret;
if (is_mt7928(&dev->mt76))
mt7928_dma_shdl_lite_init(dev);
netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
mt792x_poll_tx);
napi_enable(&dev->mt76.tx_napi);
@ -402,14 +477,18 @@ static int mt7925_pci_probe(struct pci_dev *pdev,
if (ret < 0)
return ret;
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
goto err_free_pci_vec;
is_mt7927_hw = (pdev->device == 0x6639 || pdev->device == 0x7927 ||
pdev->device == 0x0738);
is_mt7928_hw = (pdev->device == 0x7928 || pdev->device == 0x7935);
if (is_mt7928_hw)
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(34));
else
ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
goto err_free_pci_vec;
/* MT7927: ASPM L1 causes unreliable WFDMA register access */
if (mt7925_disable_aspm || is_mt7927_hw)
mt76_pci_disable_aspm(pdev);
@ -499,7 +578,7 @@ static int mt7925_pci_probe(struct pci_dev *pdev,
if (is_mt7927(&dev->mt76))
ret = mt7927_dma_init(dev);
else if (is_mt7925(&dev->mt76))
else if (is_mt7925(&dev->mt76) || is_mt7928(&dev->mt76))
ret = mt7925_dma_init(dev);
else
ret = -EINVAL;

21
drivers/net/wireless/mediatek/mt76/mt7925/regs.h
View File

@ -108,4 +108,25 @@
#define MT7925_PCIE_MAC_INT_ENABLE MT7925_PCIE_MAC(0x188)
#define MT7925_PCIE_MAC_PM MT7925_PCIE_MAC(0x194)
#define MT_DMASHDL_LITE_BASE 0x20026200
#define MT_DMASHDL_LITE(ofs) (MT_DMASHDL_LITE_BASE + (ofs))
#define MT_DMASHDL_LITE_MAIN_CONTROL MT_DMASHDL_LITE(0x004)
#define MT_DMASHDL_LITE_MAIN_CONTROL_SW_RST BIT(18)
#define MT_DMASHDL_LITE_PAGE_SIZE MT_DMASHDL_LITE(0x008)
#define MT_DMASHDL_LITE_PLE_PAGE_SIZE_MASK GENMASK(12, 0)
#define MT_DMASHDL_LITE_PSE_PAGE_SIZE_MASK GENMASK(28, 16)
#define MT_DMASHDL_LITE_PKT_MAX_SIZE MT_DMASHDL_LITE(0x00c)
#define MT_DMASHDL_LITE_PLE_PKT_MAX_SIZE_MASK GENMASK(12, 0)
#define MT_DMASHDL_LITE_PSE_PKT_MAX_SIZE_MASK GENMASK(28, 16)
#define MT_DMASHDL_LITE_GROUP_DISABLE0 MT_DMASHDL_LITE(0x010)
#define MT_DMASHDL_LITE_GROUP_DISABLE1 MT_DMASHDL_LITE(0x014)
#define MT_DMASHDL_LITE_GROUP_SN_CHK0 MT_DMASHDL_LITE(0x018)
#define MT_DMASHDL_LITE_GROUP_SN_CHK1 MT_DMASHDL_LITE(0x01c)
#define MT_DMASHDL_LITE_GROUP_UDF_CHK0 MT_DMASHDL_LITE(0x020)
#define MT_DMASHDL_LITE_GROUP_UDF_CHK1 MT_DMASHDL_LITE(0x024)
#define MT_DMASHDL_LITE_Q_MAPPING0 MT_DMASHDL_LITE(0x028)
#define MT_DMASHDL_LITE_GROUP0_QUOTA MT_DMASHDL_LITE(0x100)
#define MT_DMASHDL_LITE_GROUP_MIN_QUOTA_MASK GENMASK(12, 0)
#define MT_DMASHDL_LITE_GROUP_MAX_QUOTA_MASK GENMASK(28, 16)
#endif

94
drivers/net/wireless/mediatek/mt76/mt792x_dma.c
View File

@ -206,9 +206,38 @@ static void mt7927_wfdma_setup(struct mt792x_dev *dev)
mt76_set(dev, MT_WFDMA0_INT_TX_PRI, 0x7F00);
}
static void mt7928_dma_prefetch_setup(struct mt792x_dev *dev)
{
/* rx ring */
mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0000, 0x8));
mt76_wr(dev, MT_WFDMA0_RX_RING1_EXT_CTRL, PREFETCH(0x0080, 0x4));
mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x00c0, 0x8));
mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x0140, 0x4));
mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0x0180, 0x4));
mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x01c0, 0x4));
mt76_wr(dev, MT_WFDMA0_RX_RING6_EXT_CTRL, PREFETCH(0x0200, 0x4));
/* tx ring */
mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x0240, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x0340, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x0440, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x0540, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x0640, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x0740, 0x10));
mt76_wr(dev, MT_WFDMA0_TX_RING15_EXT_CTRL, PREFETCH(0x0840, 0x4));
mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x0880, 0x4));
}
static void mt7928_wfdma_setup(struct mt792x_dev *dev)
{
mt76_wr(dev, MT_WFDMA0_INT_RX_PRI, 0);
mt76_wr(dev, MT_WFDMA0_INT_TX_PRI, 0);
}
static void mt792x_dma_prefetch(struct mt792x_dev *dev)
{
if (is_mt7927(&dev->mt76)) {
if (is_mt7928(&dev->mt76)) {
mt7928_dma_prefetch_setup(dev);
} else if (is_mt7927(&dev->mt76)) {
mt7927_dma_prefetch_setup(dev);
} else if (is_mt7925(&dev->mt76)) {
mt7925_dma_prefetch_setup(dev);
@ -250,32 +279,69 @@ static void mt792x_dma_prefetch(struct mt792x_dev *dev)
int mt792x_dma_enable(struct mt792x_dev *dev)
{
/* configure perfetch settings */
u32 addr;
/* configure prefetch settings */
mt792x_dma_prefetch(dev);
/* reset dma idx */
mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
if (is_mt7925(&dev->mt76))
if (is_mt7925(&dev->mt76) || is_mt7928(&dev->mt76))
mt76_wr(dev, MT_WFDMA0_RST_DRX_PTR, ~0);
/* configure delay interrupt */
mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
FIELD_PREP(MT_WFDMA0_GLO_CFG_DMA_SIZE, 3) |
MT_WFDMA0_GLO_CFG_FIFO_DIS_CHECK |
MT_WFDMA0_GLO_CFG_RX_WB_DDONE |
MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
if (is_mt7928(&dev->mt76)) {
mt76_wr(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
FIELD_PREP(MT_WFDMA0_GLO_CFG_DMA_SIZE, 1) |
MT_WFDMA0_GLO_CFG_FIFO_DIS_CHECK |
MT_WFDMA0_GLO_CFG_RX_WB_DDONE |
MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
MT_WFDMA0_GLO_CFG_ADDR_EXT_EN |
MT_WFDMA0_GLO_CFG_CSR_LBK_RX_Q_SEL_EN);
/* set rxq threshold to 2 */
for (addr = MT_WFDMA0_WPDMA_PAUSE_RXQ_TH10;
addr <= MT_WFDMA0_WPDMA_PAUSE_RXQ_TH76;
addr += 4) {
mt76_wr(dev, addr,
FIELD_PREP(MT_WFDMA0_WPDMA_PAUSE_RXQ_THXX_L_TH_MASK, 2) |
FIELD_PREP(MT_WFDMA0_WPDMA_PAUSE_RXQ_THXX_H_TH_MASK, 2));
}
mt76_wr(dev, MT_WFDMA0_GLO_CFG_EXT0,
MT_WFDMA0_GLO_CFG_EXT0_CSR_MEM_ARB_LOCK_EN |
MT_WFDMA0_GLO_CFG_EXT0_CSR_TX_DMASHDL_LITE_EN |
MT_WFDMA0_GLO_CFG_EXT0_CSR_RX_WB_KEEP_RSVD |
MT_WFDMA0_GLO_CFG_EXT0_CSR_BID_CHECK_BYPASS_EN |
MT_WFDMA0_GLO_CFG_EXT0_CSR_RX_INFO_WB_EN |
MT_WFDMA0_GLO_CFG_EXT0_CSR_AXI_AWUSER_LOCK_EN |
FIELD_PREP(MT_WFDMA0_GLO_CFG_EXT0_CSR_MAX_PREFETCH_CNT_MASK, 3) |
FIELD_PREP(MT_WFDMA0_GLO_CFG_EXT0_CSR_MEM_BST_SIZE_MASK, 3) |
FIELD_PREP(MT_WFDMA0_GLO_CFG_EXT0_CSR_AXI_AW_OUTSTANDING_NUM_MASK,
8));
} else {
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
FIELD_PREP(MT_WFDMA0_GLO_CFG_DMA_SIZE, 3) |
MT_WFDMA0_GLO_CFG_FIFO_DIS_CHECK |
MT_WFDMA0_GLO_CFG_RX_WB_DDONE |
MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
}
mt76_set(dev, MT_WFDMA0_GLO_CFG,
MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
if (is_mt7927(&dev->mt76))
if (is_mt7928(&dev->mt76))
mt7928_wfdma_setup(dev);
else if (is_mt7927(&dev->mt76))
mt7927_wfdma_setup(dev);
else if (is_mt7925(&dev->mt76))
mt7925_wfdma_setup(dev);

19
drivers/net/wireless/mediatek/mt76/mt792x_regs.h
View File

@ -331,11 +331,29 @@
#define MT_INT_MCU_CMD MCU2HOST_SW_INT_ENA
#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_TH10 MT_WFDMA0(0x260)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_TH32 MT_WFDMA0(0x264)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_TH54 MT_WFDMA0(0x268)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_TH76 MT_WFDMA0(0x26c)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_THXX_L_TH_MASK GENMASK(11, 0)
#define MT_WFDMA0_WPDMA_PAUSE_RXQ_THXX_H_TH_MASK GENMASK(27, 16)
#define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280)
#define MT_WFDMA0_INT_RX_PRI MT_WFDMA0(0x298)
#define MT_WFDMA0_INT_TX_PRI MT_WFDMA0(0x29c)
#define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_MEM_ARB_LOCK_EN BIT(4)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_TX_DMASHDL_EN BIT(6)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_TX_DMASHDL_LITE_EN BIT(7)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_RX_WB_KEEP_RSVD BIT(10)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_BID_CHECK_BYPASS_EN BIT(22)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_RX_INFO_WB_EN BIT(23)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_AXI_AWUSER_LOCK_EN BIT(29)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_MAX_PREFETCH_CNT_MASK GENMASK(1, 0)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_MEM_BST_SIZE_MASK GENMASK(3, 2)
#define MT_WFDMA0_GLO_CFG_EXT0_CSR_AXI_AW_OUTSTANDING_NUM_MASK GENMASK(27, 24)
#define MT_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
#define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600)
@ -375,7 +393,6 @@
#define MT_WFDMA_PREFETCH_CFG1 MT_WFDMA_EXT_CSR(0xf4)
#define MT_WFDMA_PREFETCH_CFG2 MT_WFDMA_EXT_CSR(0xf8)
#define MT_WFDMA_PREFETCH_CFG3 MT_WFDMA_EXT_CSR(0xfc)
#define MT_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
#define MT_SWDEF_BASE 0x41f200
#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))