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clk: samsung: exynos990: Fix PERIS gate clock parents

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Correct eight PERIS gate clock parents to match the hardware clock
tree and reorder the GIC mux parents so mout_peris_bus_user is the
default source.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20260613-exynos990-peris-fix-v3-v3-3-2b230db78ae4@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Denzeel Oliva 2026-06-13 07:36:18 -05:00 committed by Krzysztof Kozlowski
parent b7d6221aa4
commit a016e89781
1 changed files with 9 additions and 9 deletions
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18
drivers/clk/samsung/clk-exynos990.c
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@ -2551,7 +2551,7 @@ static const unsigned long peris_clk_regs[] __initconst = {
/* Parent clock list for CMU_PERIS muxes */
PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" };
PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
PNAME(mout_peris_clk_peris_gic_p) = { "mout_peris_bus_user", "oscclk" };
static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
@ -2584,15 +2584,15 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
"gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
"gout_peris_clk_peris_oscclk_clk", "oscclk",
CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
"gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
"gout_peris_clk_peris_gic_clk", "mout_peris_clk_peris_gic",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
"gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
"gout_peris_ad_axi_p_peris_aclkm", "mout_peris_clk_peris_gic",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
@ -2600,19 +2600,19 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_GIC_CLK,
"gout_peris_gic_clk", "mout_peris_bus_user",
"gout_peris_gic_clk", "mout_peris_clk_peris_gic",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
"gout_peris_lhm_axi_p_peris_clk", "oscclk",
"gout_peris_lhm_axi_p_peris_clk", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_PERIS_MCT_PCLK,
"gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
"gout_peris_mct_pclk", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
"gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
"gout_peris_otp_con_top_pclk", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
@ -2624,7 +2624,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
"gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
"gout_peris_tmu_top_pclk", "mout_peris_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
21, 0, 0),
GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,