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drm/amd/display: Update DML2.1 generated code

Browse Source 
Most of the DML code is generated, and it is necessary to update some
parts of it from time to time. This commit brings the latest generated
code for DML 2.1.

Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2024-04-29 14:07:50 -04:00 committed by Alex Deucher
parent 91b586cc05
commit a00e85713c
25 changed files with 2067 additions and 1177 deletions
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19
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
View File

@ -338,7 +338,8 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in
}
static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,
struct dc_stream_state *stream)
struct dc_stream_state *stream,
struct dml2_context *dml_ctx)
{
unsigned int hblank_start, vblank_start;
@ -372,7 +373,12 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
timing->drr_config.drr_active_variable = stream->vrr_active_variable;
timing->drr_config.drr_active_fixed = stream->vrr_active_fixed;
timing->drr_config.disallowed = !stream->allow_freesync;
//timing->drr_config.max_instant_vtotal_delta = timing-><drr no flicker delta lum>;
if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&
stream->ctx->dc->config.enable_fpo_flicker_detection == 1)
timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);
else
timing->drr_config.max_instant_vtotal_delta = 0;
if (stream->timing.flags.DSC) {
timing->dsc.enable = dml2_dsc_enable;
@ -505,7 +511,8 @@ static void populate_dml21_stream_overrides_from_stream_state(
stream_desc->overrides.odm_mode = dml2_odm_mode_auto;
break;
}
if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy)
if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy ||
stream->debug.force_odm_combine_segments > 0)
stream_desc->overrides.disable_dynamic_odm = true;
stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp;
}
@ -699,7 +706,7 @@ static const struct scaler_data *get_scaler_data_for_plane(
temp_pipe->stream = pipe->stream;
temp_pipe->plane_state = pipe->plane_state;
temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
temp_pipe->stream_res = pipe->stream_res;
dml_ctx->config.callbacks.build_scaling_params(temp_pipe);
break;
}
@ -956,7 +963,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
disp_cfg_stream_location = dml_dispcfg->num_streams++;
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index]);
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);
populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);
populate_dml21_stream_overrides_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index]);
@ -1007,6 +1014,8 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.dcfclk_khz;
context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.uclk_khz;
context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.active.fclk_khz;
context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.idle.uclk_khz;
context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.idle.fclk_khz;
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4.deepsleep_dcfclk_khz;
context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming->fclk_pstate_supported;
context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported;

2
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
View File

@ -59,7 +59,7 @@ static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_contex
pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||
in_dc->debug.force_disable_subvp ||
disable_fams2;
pmo_options->disable_drr_fixed = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||
pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||
disable_fams2;
pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||
disable_fams2;

27
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h
View File

@ -120,11 +120,11 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = {
.num_clk_values = 2,
},
.phyclk_d18 = {
.clk_values_khz = {667000, 667000},
.clk_values_khz = {625000, 625000},
.num_clk_values = 2,
},
.phyclk_d32 = {
.clk_values_khz = {2000000, 2000000},
.clk_values_khz = {625000, 625000},
.num_clk_values = 2,
},
.dram_config = {
@ -289,17 +289,29 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = {
.dram_clk_change_blackout_us = 400,
.fclk_change_blackout_us = 0,
.g7_ppt_blackout_us = 0,
.stutter_enter_plus_exit_latency_us = 21,
.stutter_exit_latency_us = 16,
.stutter_enter_plus_exit_latency_us = 54,
.stutter_exit_latency_us = 41,
.z8_stutter_enter_plus_exit_latency_us = 0,
.z8_stutter_exit_latency_us = 0,
/*
.g6_temp_read_blackout_us = {
23.00,
10.00,
10.00,
8.00,
8.00,
5.00,
5.00,
5.00,
},
*/
},
.vmin_limit = {
.dispclk_khz = 600 * 1000,
},
.dprefclk_mhz = 700,
.dprefclk_mhz = 720,
.xtalclk_mhz = 100,
.pcie_refclk_mhz = 100,
.dchub_refclk_mhz = 50,
@ -309,8 +321,8 @@ static const struct dml2_soc_bb dml2_socbb_dcn401 = {
.return_bus_width_bytes = 64,
.hostvm_min_page_size_kbytes = 0,
.gpuvm_min_page_size_kbytes = 256,
.phy_downspread_percent = 0,
.dcn_downspread_percent = 0,
.phy_downspread_percent = 0.38,
.dcn_downspread_percent = 0.38,
.dispclk_dppclk_vco_speed_mhz = 4500,
.do_urgent_latency_adjustment = 0,
.mem_word_bytes = 32,
@ -329,6 +341,7 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = {
.max_num_dp2p0_outputs = 4,
.rob_buffer_size_kbytes = 192,
.config_return_buffer_size_in_kbytes = 1344,
.config_return_buffer_segment_size_in_kbytes = 64,
.meta_fifo_size_in_kentries = 22,
.compressed_buffer_segment_size_in_kbytes = 64,
.subvp_drr_scheduling_margin_us = 100,

9
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h
View File

@ -380,7 +380,11 @@ struct dml2_plane_parameters {
enum dml2_refresh_from_mall_mode_override refresh_from_mall;
unsigned int det_size_override_kb;
unsigned int mpcc_combine_factor;
long reserved_vblank_time_ns; // 0 = no override, -ve = no reserved time, +ve = explicit reserved time
// reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait
// The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override.
long reserved_vblank_time_ns;
unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay
unsigned int gpuvm_min_page_size_kbytes;
enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config
@ -407,6 +411,7 @@ struct dml2_stream_parameters {
enum dml2_odm_mode odm_mode;
bool disable_dynamic_odm;
bool disable_subvp;
bool disable_fams2_drr;
int minimum_vblank_idle_requirement_us;
bool minimize_active_latency_hiding;
@ -429,7 +434,7 @@ struct dml2_display_cfg {
bool minimize_det_reallocation;
unsigned int gpuvm_max_page_table_levels;
unsigned int hostvm_max_page_table_levels;
unsigned int hostvm_max_non_cached_page_table_levels;
struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];
struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];

3
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
View File

@ -169,8 +169,11 @@ struct dml2_ip_capabilities {
unsigned int max_num_dp2p0_outputs;
unsigned int rob_buffer_size_kbytes;
unsigned int config_return_buffer_size_in_kbytes;
unsigned int config_return_buffer_segment_size_in_kbytes;
unsigned int meta_fifo_size_in_kentries;
unsigned int compressed_buffer_segment_size_in_kbytes;
unsigned int max_flip_time_us;
unsigned int hostvm_mode;
unsigned int subvp_drr_scheduling_margin_us;
unsigned int subvp_prefetch_end_to_mall_start_us;
unsigned int subvp_fw_processing_delay;

6
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h
View File

@ -72,9 +72,10 @@ struct dml2_pmo_options {
bool disable_vblank;
bool disable_svp;
bool disable_drr_var;
bool disable_drr_fixed;
bool disable_drr_clamped;
bool disable_drr_var_when_var_active;
bool disable_fams2;
bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */
bool disable_dyn_odm;
bool disable_dyn_odm_for_multi_stream;
bool disable_dyn_odm_for_stream_with_svp;
@ -331,7 +332,6 @@ struct dml2_mode_support_info {
bool DTBCLKRequiredMoreThanSupported;
bool LinkCapacitySupport;
bool ROBSupport;
bool ROBUrgencyAvoidance;
bool OutstandingRequestsSupport;
bool OutstandingRequestsUrgencyAvoidance;
bool PTEBufferSizeNotExceeded;
@ -659,6 +659,7 @@ struct dml2_display_cfg_programming {
double DSCDelay[DML2_MAX_PLANES];
double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY
bool ROBUrgencyAvoidance;
} misc;
struct dml2_mode_support_info mode_support_info;
@ -715,4 +716,5 @@ struct dml2_unit_test_in_out {
struct dml2_instance *dml2_instance;
};
#endif

112
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
View File

@ -66,7 +66,6 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = {
.cursor_64bpp_support = true,
.dynamic_metadata_vm_enabled = false,
.max_num_hdmi_frl_outputs = 1,
.max_num_dp2p0_outputs = 4,
.max_num_dp2p0_streams = 4,
.imall_supported = 1,
@ -78,6 +77,84 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = {
.subvp_swath_height_margin_lines = 16,
};
struct dml2_core_ip_params core_dcn4sw_ip_caps_base = {
.vblank_nom_default_us = 668,
.remote_iommu_outstanding_translations = 256,
.rob_buffer_size_kbytes = 192,
.config_return_buffer_size_in_kbytes = 1280,
.config_return_buffer_segment_size_in_kbytes = 64,
.compressed_buffer_segment_size_in_kbytes = 64,
.dpte_buffer_size_in_pte_reqs_luma = 68,
.dpte_buffer_size_in_pte_reqs_chroma = 36,
.pixel_chunk_size_kbytes = 8,
.alpha_pixel_chunk_size_kbytes = 4,
.min_pixel_chunk_size_bytes = 1024,
.writeback_chunk_size_kbytes = 8,
.line_buffer_size_bits = 1171920,
.max_line_buffer_lines = 32,
.writeback_interface_buffer_size_kbytes = 90,
//Number of pipes after DCN Pipe harvesting
.max_num_dpp = 4,
.max_num_otg = 4,
.max_num_wb = 1,
.max_dchub_pscl_bw_pix_per_clk = 4,
.max_pscl_lb_bw_pix_per_clk = 2,
.max_lb_vscl_bw_pix_per_clk = 4,
.max_vscl_hscl_bw_pix_per_clk = 4,
.max_hscl_ratio = 6,
.max_vscl_ratio = 6,
.max_hscl_taps = 8,
.max_vscl_taps = 8,
.dispclk_ramp_margin_percent = 1,
.dppclk_delay_subtotal = 47,
.dppclk_delay_scl = 50,
.dppclk_delay_scl_lb_only = 16,
.dppclk_delay_cnvc_formatter = 28,
.dppclk_delay_cnvc_cursor = 6,
.cursor_buffer_size = 24,
.cursor_chunk_size = 2,
.dispclk_delay_subtotal = 125,
.max_inter_dcn_tile_repeaters = 8,
.writeback_max_hscl_ratio = 1,
.writeback_max_vscl_ratio = 1,
.writeback_min_hscl_ratio = 1,
.writeback_min_vscl_ratio = 1,
.writeback_max_hscl_taps = 1,
.writeback_max_vscl_taps = 1,
.writeback_line_buffer_buffer_size = 0,
.num_dsc = 4,
.maximum_dsc_bits_per_component = 12,
.maximum_pixels_per_line_per_dsc_unit = 5760,
.dsc422_native_support = true,
.dcc_supported = true,
.ptoi_supported = false,
.cursor_64bpp_support = true,
.dynamic_metadata_vm_enabled = false,
.max_num_hdmi_frl_outputs = 1,
.max_num_dp2p0_outputs = 4,
.max_num_dp2p0_streams = 4,
.imall_supported = 1,
.max_flip_time_us = 80,
.words_per_channel = 16,
.subvp_fw_processing_delay_us = 15,
.subvp_pstate_allow_width_us = 20,
.subvp_swath_height_margin_lines = 16,
.dcn_mrq_present = 1,
.zero_size_buffer_entries = 512,
.compbuf_reserved_space_zs = 64,
.dcc_meta_buffer_size_bytes = 6272,
.meta_chunk_size_kbytes = 2,
.min_meta_chunk_size_bytes = 256,
.dchub_arb_to_ret_delay = 102,
.hostvm_mode = 1,
};
static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params)
{
ip_caps->pipe_count = ip_params->max_num_dpp;
@ -85,10 +162,14 @@ static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *i
ip_caps->num_dsc = ip_params->num_dsc;
ip_caps->max_num_dp2p0_streams = ip_params->max_num_dp2p0_streams;
ip_caps->max_num_dp2p0_outputs = ip_params->max_num_dp2p0_outputs;
ip_caps->max_num_hdmi_frl_outputs = ip_params->max_num_hdmi_frl_outputs;
ip_caps->rob_buffer_size_kbytes = ip_params->rob_buffer_size_kbytes;
ip_caps->config_return_buffer_size_in_kbytes = ip_params->config_return_buffer_size_in_kbytes;
ip_caps->config_return_buffer_segment_size_in_kbytes = ip_params->config_return_buffer_segment_size_in_kbytes;
ip_caps->meta_fifo_size_in_kentries = ip_params->meta_fifo_size_in_kentries;
ip_caps->compressed_buffer_segment_size_in_kbytes = ip_params->compressed_buffer_segment_size_in_kbytes;
ip_caps->max_flip_time_us = ip_params->max_flip_time_us;
ip_caps->hostvm_mode = ip_params->hostvm_mode;
// FIXME_STAGE2: cleanup after adding all dv override to ip_caps
ip_caps->subvp_drr_scheduling_margin_us = 100;
@ -104,10 +185,14 @@ static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params,
ip_params->num_dsc = ip_caps->num_dsc;
ip_params->max_num_dp2p0_streams = ip_caps->max_num_dp2p0_streams;
ip_params->max_num_dp2p0_outputs = ip_caps->max_num_dp2p0_outputs;
ip_params->max_num_hdmi_frl_outputs = ip_caps->max_num_hdmi_frl_outputs;
ip_params->rob_buffer_size_kbytes = ip_caps->rob_buffer_size_kbytes;
ip_params->config_return_buffer_size_in_kbytes = ip_caps->config_return_buffer_size_in_kbytes;
ip_params->config_return_buffer_segment_size_in_kbytes = ip_caps->config_return_buffer_segment_size_in_kbytes;
ip_params->meta_fifo_size_in_kentries = ip_caps->meta_fifo_size_in_kentries;
ip_params->compressed_buffer_segment_size_in_kbytes = ip_caps->compressed_buffer_segment_size_in_kbytes;
ip_params->max_flip_time_us = ip_caps->max_flip_time_us;
ip_params->hostvm_mode = ip_caps->hostvm_mode;
}
bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out)
@ -343,14 +428,12 @@ static void pack_mode_programming_params_with_implicit_subvp(struct dml2_core_in
programming->stream_programming[main_plane->stream_index].uclk_pstate_method = programming->plane_programming[plane_index].uclk_pstate_support_method;
// If FAMS2 is required, populate stream params
if (programming->fams2_required) {
dml2_core_calcs_get_stream_fams2_programming(&core->clean_me_up.mode_lib,
display_cfg,
&programming->stream_programming[main_plane->stream_index].fams2_params,
programming->stream_programming[main_plane->stream_index].uclk_pstate_method,
plane_index);
}
/* unconditionally populate fams2 params */
dml2_core_calcs_get_stream_fams2_programming(&core->clean_me_up.mode_lib,
display_cfg,
&programming->stream_programming[main_plane->stream_index].fams2_params,
programming->stream_programming[main_plane->stream_index].uclk_pstate_method,
plane_index);
stream_already_populated_mask |= (0x1 << main_plane->stream_index);
}
@ -394,7 +477,7 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
bool result;
unsigned int i, stream_index, stream_bitmask;
int unsigned odm_count, dpp_count;
int unsigned odm_count, num_odm_output_segments, dpp_count;
expand_implict_subvp(in_out->display_cfg, &l->svp_expanded_display_cfg, &core->scratch);
@ -448,6 +531,10 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
stream_bitmask = 0;
for (i = 0; i < l->svp_expanded_display_cfg.num_planes; i++) {
odm_count = 1;
dpp_count = l->mode_support_ex_params.out_evaluation_info->DPPPerSurface[i];
num_odm_output_segments = 1;
switch (l->mode_support_ex_params.out_evaluation_info->ODMMode[i]) {
case dml2_odm_mode_bypass:
odm_count = 1;
@ -467,7 +554,11 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
break;
case dml2_odm_mode_split_1to2:
case dml2_odm_mode_mso_1to2:
num_odm_output_segments = 2;
break;
case dml2_odm_mode_mso_1to4:
num_odm_output_segments = 4;
break;
case dml2_odm_mode_auto:
default:
odm_count = 1;
@ -486,6 +577,7 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
if (!((stream_bitmask >> stream_index) & 0x1)) {
in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index].odms_used = odm_count;
in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index].num_odm_output_segments = num_odm_output_segments;
in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index].dsc_enable = l->mode_support_ex_params.out_evaluation_info->DSCEnabled[i];
in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index].num_dsc_slices = l->mode_support_ex_params.out_evaluation_info->NumberOfDSCSlices[i];
dml2_core_calcs_get_stream_support_info(&l->svp_expanded_display_cfg, &core->clean_me_up.mode_lib, &in_out->mode_support_result.cfg_support_info.stream_support_info[stream_index], i);

2261
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
View File

File diff suppressed because it is too large Load Diff

176
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
View File

@ -8,8 +8,6 @@
#include "dml2_debug.h"
#include "lib_float_math.h"
#define DML2_MAX_FMT_420_BUFFER_WIDTH 4096
double dml2_core_shared_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)
{
*remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0);
@ -372,7 +370,6 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch
static void CalculateODMMode(
unsigned int MaximumPixelsPerLinePerDSCUnit,
unsigned int HActive,
enum dml2_output_format_class OutFormat,
enum dml2_output_encoder_class Output,
enum dml2_odm_mode ODMUse,
double MaxDispclk,
@ -861,6 +858,7 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
mode_lib->ms.support.ScaleRatioAndTapsSupport = false;
}
}
/*Source Format, Pixel Format and Scan Support Check*/
mode_lib->ms.support.SourceFormatPixelAndScanSupport = true;
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
@ -1189,7 +1187,6 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
CalculateODMMode(
mode_lib->ip.maximum_pixels_per_line_per_dsc_unit,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
mode_lib->ms.max_dispclk_freq_mhz,
@ -1207,7 +1204,6 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
CalculateODMMode(
mode_lib->ip.maximum_pixels_per_line_per_dsc_unit,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder,
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].overrides.odm_mode,
mode_lib->ms.max_dispclk_freq_mhz,
@ -1389,6 +1385,8 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
if (display_cfg->plane_descriptors[k].stream_index == k) {
s->TotalNumberOfActiveOTG = s->TotalNumberOfActiveOTG + 1;
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl)
s->TotalNumberOfActiveHDMIFRL = s->TotalNumberOfActiveHDMIFRL + 1;
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_dp2p0) {
s->TotalNumberOfActiveDP2p0 = s->TotalNumberOfActiveDP2p0 + 1;
// FIXME_STAGE2: SW not using backend related stuff, need mapping for mst setup
@ -1400,6 +1398,7 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
}
mode_lib->ms.support.NumberOfOTGSupport = (s->TotalNumberOfActiveOTG <= (unsigned int)mode_lib->ip.max_num_otg);
mode_lib->ms.support.NumberOfHDMIFRLSupport = (s->TotalNumberOfActiveHDMIFRL <= (unsigned int)mode_lib->ip.max_num_hdmi_frl_outputs);
mode_lib->ms.support.NumberOfDP2p0Support = (s->TotalNumberOfActiveDP2p0 <= (unsigned int)mode_lib->ip.max_num_dp2p0_streams && s->TotalNumberOfActiveDP2p0Outputs <= (unsigned int)mode_lib->ip.max_num_dp2p0_outputs);
mode_lib->ms.support.ExceededMultistreamSlots = false;
@ -1984,60 +1983,14 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
dml2_printf("DML::%s: FullFrameMALLPStateMethod = %u\n", __func__, s->FullFrameMALLPStateMethod);
dml2_printf("DML::%s: SubViewportMALLRefreshGreaterThan120Hz = %u\n", __func__, s->SubViewportMALLRefreshGreaterThan120Hz);
dml2_printf("DML::%s: InvalidCombinationOfMALLUseForPState = %u\n", __func__, mode_lib->ms.support.InvalidCombinationOfMALLUseForPState);
#endif
//Re-ordering Buffer Support Check
mode_lib->ms.support.max_non_urgent_latency_us
= mode_lib->soc.qos_parameters.qos_params.dcn4.per_uclk_dpm_params[mode_lib->ms.qos_param_index].maximum_latency_when_non_urgent_uclk_cycles / mode_lib->ms.uclk_freq_mhz
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.umc_max_latency_margin / 100.0)
+ mode_lib->soc.qos_parameters.qos_params.dcn4.mall_overhead_fclk_cycles / mode_lib->ms.FabricClock
+ mode_lib->soc.qos_parameters.qos_params.dcn4.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->ms.FabricClock
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.fabric_max_transport_latency_margin / 100.0);
mode_lib->ms.support.max_urgent_latency_us
= mode_lib->soc.qos_parameters.qos_params.dcn4.per_uclk_dpm_params[mode_lib->ms.qos_param_index].maximum_latency_when_urgent_uclk_cycles / mode_lib->ms.uclk_freq_mhz
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.umc_max_latency_margin / 100.0)
+ mode_lib->soc.qos_parameters.qos_params.dcn4.mall_overhead_fclk_cycles / mode_lib->ms.FabricClock
+ mode_lib->soc.qos_parameters.qos_params.dcn4.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->ms.FabricClock
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.fabric_max_transport_latency_margin / 100.0);
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4) {
if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024
/ (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)) >= mode_lib->ms.support.max_urgent_latency_us) {
mode_lib->ms.support.ROBSupport = true;
} else {
mode_lib->ms.support.ROBSupport = false;
}
} else {
if (mode_lib->ip.rob_buffer_size_kbytes * 1024 >= mode_lib->soc.qos_parameters.qos_params.dcn3.loaded_round_trip_latency_fclk_cycles * mode_lib->soc.fabric_datapath_to_dcn_data_return_bytes) {
mode_lib->ms.support.ROBSupport = true;
} else {
mode_lib->ms.support.ROBSupport = false;
}
}
#ifdef __DML_VBA_DEBUG__
dml2_printf("DML::%s: in_out_params->min_clk_index = %u\n", __func__, in_out_params->min_clk_index);
dml2_printf("DML::%s: mode_lib->ms.DCFCLK = %f\n", __func__, mode_lib->ms.DCFCLK);
dml2_printf("DML::%s: mode_lib->ms.FabricClock = %f\n", __func__, mode_lib->ms.FabricClock);
dml2_printf("DML::%s: mode_lib->ms.uclk_freq_mhz = %f\n", __func__, mode_lib->ms.uclk_freq_mhz);
dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.max_urgent_latency_us);
dml2_printf("DML::%s: urgent latency tolerance = %f\n", __func__, ((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)));
dml2_printf("DML::%s: ROBSupport = %u\n", __func__, mode_lib->ms.support.ROBSupport);
dml2_printf("DML::%s: urgent latency tolarance = %f\n", __func__, ((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024 / (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)));
#endif
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4) {
if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024
/ (mode_lib->ms.DCFCLK * mode_lib->soc.return_bus_width_bytes)) >= mode_lib->ms.support.max_non_urgent_latency_us) {
mode_lib->ms.support.ROBUrgencyAvoidance = true;
} else {
mode_lib->ms.support.ROBUrgencyAvoidance = false;
}
} else {
mode_lib->ms.support.ROBUrgencyAvoidance = true;
}
mode_lib->ms.support.OutstandingRequestsSupport = true;
mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance = true;
@ -2762,6 +2715,34 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
dml2_printf("DML::%s: Done prefetch calculation\n", __func__);
//Re-ordering Buffer Support Check
mode_lib->ms.support.max_urgent_latency_us
= mode_lib->soc.qos_parameters.qos_params.dcn4.per_uclk_dpm_params[mode_lib->ms.qos_param_index].maximum_latency_when_urgent_uclk_cycles / mode_lib->ms.uclk_freq_mhz
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.umc_max_latency_margin / 100.0)
+ mode_lib->soc.qos_parameters.qos_params.dcn4.mall_overhead_fclk_cycles / mode_lib->ms.FabricClock
+ mode_lib->soc.qos_parameters.qos_params.dcn4.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->ms.FabricClock
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.fabric_max_transport_latency_margin / 100.0);
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4) {
if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024
/ mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= mode_lib->ms.support.max_urgent_latency_us) {
mode_lib->ms.support.ROBSupport = true;
} else {
mode_lib->ms.support.ROBSupport = false;
}
} else {
if (mode_lib->ip.rob_buffer_size_kbytes * 1024 >= mode_lib->soc.qos_parameters.qos_params.dcn3.loaded_round_trip_latency_fclk_cycles * mode_lib->soc.fabric_datapath_to_dcn_data_return_bytes) {
mode_lib->ms.support.ROBSupport = true;
} else {
mode_lib->ms.support.ROBSupport = false;
}
}
#ifdef __DML_VBA_DEBUG__
dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.max_urgent_latency_us);
dml2_printf("DML::%s: ROBSupport = %u\n", __func__, mode_lib->ms.support.ROBSupport);
#endif
/*Mode Support, Voltage State and SOC Configuration*/
{
// s->dram_clock_change_support = 1;
@ -2790,7 +2771,6 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
&& !mode_lib->ms.support.DTBCLKRequiredMoreThanSupported
&& !mode_lib->ms.support.InvalidCombinationOfMALLUseForPState
&& mode_lib->ms.support.ROBSupport
&& mode_lib->ms.support.ROBUrgencyAvoidance
&& mode_lib->ms.support.OutstandingRequestsSupport
&& mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance
&& mode_lib->ms.support.DISPCLK_DPPCLK_Support
@ -2937,8 +2917,6 @@ static void dml2_print_dml_mode_support_info(const struct dml2_core_internal_mod
dml2_printf("DML: support: LinkCapacitySupport = 0x%x\n", support->LinkCapacitySupport);
if (!fail_only || support->ROBSupport == 0)
dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport);
if (!fail_only || support->ROBUrgencyAvoidance == 0)
dml2_printf("DML: support: ROBUrgencyAvoidance = %d\n", support->ROBUrgencyAvoidance);
if (!fail_only || support->OutstandingRequestsSupport == 0)
dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);
if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)
@ -5574,7 +5552,7 @@ static void CalculateVMRowAndSwath(struct dml2_core_internal_scratch *scratch,
{
struct dml2_core_calcs_CalculateVMRowAndSwath_locals *s = &scratch->CalculateVMRowAndSwath_locals;
s->HostVMDynamicLevels = CalculateHostVMDynamicLevels(p->display_cfg->gpuvm_enable, p->display_cfg->hostvm_enable, p->HostVMMinPageSize, p->display_cfg->hostvm_max_page_table_levels);
s->HostVMDynamicLevels = CalculateHostVMDynamicLevels(p->display_cfg->gpuvm_enable, p->display_cfg->hostvm_enable, p->HostVMMinPageSize, p->display_cfg->hostvm_max_non_cached_page_table_levels);
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
if (p->display_cfg->hostvm_enable == true) {
@ -6093,9 +6071,6 @@ static void calculate_cursor_req_attributes(
dml2_printf("DML::%s: cursor_bytes = %d\n", __func__, *cursor_bytes);
dml2_printf("DML::%s: cursor_pitch = %d\n", __func__, cursor_pitch);
#endif
// register CURSOR_PITCH = math_log2(cursor_pitch) - 6;
// register CURSOR_LINES_PER_CHUNK = math_log2(*cursor_lines_per_chunk);
}
static void calculate_cursor_urgent_burst_factor(
@ -6576,7 +6551,6 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch
static void CalculateODMMode(
unsigned int MaximumPixelsPerLinePerDSCUnit,
unsigned int HActive,
enum dml2_output_format_class OutFormat,
enum dml2_output_encoder_class Output,
enum dml2_odm_mode ODMUse,
double MaxDispclk,
@ -6602,23 +6576,6 @@ static void CalculateODMMode(
SurfaceRequiredDISPCLKWithODMCombineFourToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_4to1, PixelClock);
*TotalAvailablePipesSupport = true;
if (OutFormat == dml2_420) {
if (HActive > 4 * DML2_MAX_FMT_420_BUFFER_WIDTH)
*TotalAvailablePipesSupport = false;
else if (HActive > 3 * DML2_MAX_FMT_420_BUFFER_WIDTH)
ODMUse = dml2_odm_mode_combine_4to1;
else if (HActive > 2 * DML2_MAX_FMT_420_BUFFER_WIDTH)
ODMUse = dml2_odm_mode_combine_3to1;
else if (HActive > DML2_MAX_FMT_420_BUFFER_WIDTH)
ODMUse = dml2_odm_mode_combine_2to1;
if (Output == dml2_hdmi && ODMUse == dml2_odm_mode_combine_2to1)
*TotalAvailablePipesSupport = false;
if (Output == dml2_hdmi && ODMUse == dml2_odm_mode_combine_3to1)
*TotalAvailablePipesSupport = false;
if (Output == dml2_hdmi && ODMUse == dml2_odm_mode_combine_4to1)
*TotalAvailablePipesSupport = false;
}
if (ODMUse == dml2_odm_mode_bypass || ODMUse == dml2_odm_mode_auto)
*ODMMode = dml2_odm_mode_bypass;
else if (ODMUse == dml2_odm_mode_combine_2to1)
@ -7176,9 +7133,9 @@ static void calculate_tdlut_setting(
if (p->tdlut_addressing_mode == dml2_tdlut_simple_linear) {
if (p->tdlut_width_mode == dml2_tdlut_width_17_cube)
tdlut_width = 4916;
tdlut_width = 4916;
else
tdlut_width = 35940;
tdlut_width = 35940;
} else {
if (p->tdlut_width_mode == dml2_tdlut_width_17_cube)
tdlut_width = 17;
@ -7268,7 +7225,7 @@ static void CalculateTarb(
{
double extra_bytes = 0;
double extra_bytes_prefetch = 0;
double HostVMDynamicLevels = CalculateHostVMDynamicLevels(display_cfg->gpuvm_enable, display_cfg->hostvm_enable, HostVMMinPageSize, display_cfg->hostvm_max_page_table_levels);
double HostVMDynamicLevels = CalculateHostVMDynamicLevels(display_cfg->gpuvm_enable, display_cfg->hostvm_enable, HostVMMinPageSize, display_cfg->hostvm_max_non_cached_page_table_levels);
for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) {
extra_bytes = extra_bytes + (NumberOfDPP[k] * PixelChunkSizeInKByte * 1024);
@ -7608,7 +7565,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch
s->TWait_p = p->TWait - p->Ttrip; // TWait includes max(Turg, Ttrip)
if (p->display_cfg->gpuvm_enable == true && p->display_cfg->hostvm_enable == true) {
s->HostVMDynamicLevelsTrips = p->display_cfg->hostvm_max_page_table_levels;
s->HostVMDynamicLevelsTrips = p->display_cfg->hostvm_max_non_cached_page_table_levels;
} else {
s->HostVMDynamicLevelsTrips = 0;
}
@ -8174,7 +8131,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch
dml2_printf("DML: Tvm: %fus - time to fetch vm\n", s->TimeForFetchingVM);
dml2_printf("DML: Tr0: %fus - time to fetch first row of data pagetables\n", s->TimeForFetchingRowInVBlank);
dml2_printf("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", (double)s->LinesToRequestPrefetchPixelData * s->LineTime);
dml2_printf("DML: To: %fus - time for propagation from scaler to optc\n", (*p->DSTYAfterScaler + ((double)(*p->DSTXAfterScaler) / (double)p->myPipe->HTotal)) * s->LineTime);
dml2_printf("DML: To: %fus - time for propogation from scaler to optc\n", (*p->DSTYAfterScaler + ((double)(*p->DSTXAfterScaler) / (double)p->myPipe->HTotal)) * s->LineTime);
dml2_printf("DML: Tvstartup - TSetup - Tcalc - TWait - Tpre - To > 0\n");
dml2_printf("DML: Tslack(pre): %fus - time left over in schedule\n", p->VStartup * s->LineTime - s->TimeForFetchingVM - 2 * s->TimeForFetchingRowInVBlank - (*p->DSTYAfterScaler + ((double)(*p->DSTXAfterScaler) / (double)p->myPipe->HTotal)) * s->LineTime - p->TWait - p->TCalc - *p->TSetup);
dml2_printf("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %u\n", p->PixelPTEBytesPerRow);
@ -9871,24 +9828,32 @@ bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_e
mode_lib->mp.active_min_uclk_dpm_index = get_active_min_uclk_dpm_index(programming->min_clocks.dcn4.active.uclk_khz, &mode_lib->soc.clk_table);
for (k = 0; k < s->num_active_planes; ++k) {
switch (cfg_support_info->stream_support_info[display_cfg->plane_descriptors[k].stream_index].odms_used) {
unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;
dml2_assert(cfg_support_info->stream_support_info[stream_index].odms_used <= 4);
dml2_assert(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 4 ||
cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 2 ||
cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);
if (cfg_support_info->stream_support_info[stream_index].odms_used > 1)
dml2_assert(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);
switch (cfg_support_info->stream_support_info[stream_index].odms_used) {
case (4):
if (cfg_support_info->plane_support_info[k].dpps_used == 1)
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to2; // FIXME_STAGE2: for mode programming same as dml2_odm_mode_split_1to2?
else
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_4to1;
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_4to1;
break;
case (3):
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_3to1;
break;
case (2):
if (cfg_support_info->plane_support_info[k].dpps_used == 1)
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to4;
else
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_2to1;
mode_lib->mp.ODMMode[k] = dml2_odm_mode_combine_2to1;
break;
default:
mode_lib->mp.ODMMode[k] = dml2_odm_mode_bypass;
if (cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 4)
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to4;
else if (cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 2)
mode_lib->mp.ODMMode[k] = dml2_odm_mode_mso_1to2;
else
mode_lib->mp.ODMMode[k] = dml2_odm_mode_bypass;
break;
}
}
@ -10994,7 +10959,7 @@ bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_e
if (display_cfg->plane_descriptors[k].immediate_flip && mode_lib->mp.ImmediateFlipSupportedForPipe[k] == false) {
mode_lib->mp.ImmediateFlipSupported = false;
#ifdef __DML_VBA_DEBUG__
dml2_printf("DML::%s: Pipe %0d not supporting iflip!\n", __func__, k);
dml2_printf("DML::%s: Pipe %0d not supporing iflip!\n", __func__, k);
#endif
}
}
@ -11453,7 +11418,7 @@ static unsigned int log_and_substract_if_non_zero(unsigned int a, unsigned int s
if (a == 0)
return 0;
return (unsigned int)(math_log2((float)a) - subtrahend);
return (math_log2_approx(a) - subtrahend);
}
void dml2_core_shared_cursor_dlg_reg(struct dml2_cursor_dlg_regs *cursor_dlg_regs, const struct dml2_get_cursor_dlg_reg *p)
@ -11545,7 +11510,7 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs,
#endif
DML2_ASSERT(p0_pte_row_height_linear >= 8);
rq_regs->rq_regs_l.pte_row_height_linear = (unsigned int)(math_floor2(math_log2((float)p0_pte_row_height_linear), 1) - 3);
rq_regs->rq_regs_l.pte_row_height_linear = math_log2_approx(p0_pte_row_height_linear) - 3;
if (dual_plane) {
unsigned int p1_pte_row_height_linear = (unsigned int)(mode_lib->mp.dpte_row_height_linear_chroma[mode_lib->mp.pipe_plane[pipe_idx]]);
#ifdef __DML_VBA_DEBUG__
@ -11555,7 +11520,7 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs,
DML2_ASSERT(p1_pte_row_height_linear >= 8);
}
rq_regs->rq_regs_c.pte_row_height_linear = (unsigned int)(math_floor2(math_log2((float)p1_pte_row_height_linear), 1) - 3);
rq_regs->rq_regs_c.pte_row_height_linear = math_log2_approx(p1_pte_row_height_linear) - 3;
}
} else {
rq_regs->rq_regs_l.pte_row_height_linear = 0;
@ -12119,7 +12084,6 @@ void dml2_core_shared_get_informative(const struct dml2_core_internal_display_mo
out->informative.mode_support_info.LinkCapacitySupport = mode_lib->ms.support.LinkCapacitySupport;
out->informative.mode_support_info.ROBSupport = mode_lib->ms.support.ROBSupport;
out->informative.mode_support_info.ROBUrgencyAvoidance = mode_lib->ms.support.ROBUrgencyAvoidance;
out->informative.mode_support_info.OutstandingRequestsSupport = mode_lib->ms.support.OutstandingRequestsSupport;
out->informative.mode_support_info.OutstandingRequestsUrgencyAvoidance = mode_lib->ms.support.OutstandingRequestsUrgencyAvoidance;
out->informative.mode_support_info.PTEBufferSizeNotExceeded = mode_lib->ms.support.PTEBufferSizeNotExceeded;
@ -12211,7 +12175,6 @@ void dml2_core_shared_get_informative(const struct dml2_core_internal_display_mo
out->informative.qos.min_return_latency_in_dcfclk = mode_lib->mp.min_return_latency_in_dcfclk;
out->informative.qos.urgent_latency_us = mode_lib->mp.UrgentLatency;
out->informative.qos.max_non_urgent_latency_us = mode_lib->ms.support.max_non_urgent_latency_us;
out->informative.qos.max_urgent_latency_us = mode_lib->ms.support.max_urgent_latency_us;
out->informative.qos.avg_non_urgent_latency_us = mode_lib->ms.support.avg_non_urgent_latency_us;
out->informative.qos.avg_urgent_latency_us = mode_lib->ms.support.avg_urgent_latency_us;
@ -12408,4 +12371,21 @@ void dml2_core_shared_get_informative(const struct dml2_core_internal_display_mo
out->informative.non_optimized_mcache_allocation[k].global_mcache_ids_plane1[n] = k;
}
}
out->informative.qos.max_non_urgent_latency_us = mode_lib->soc.qos_parameters.qos_params.dcn4.per_uclk_dpm_params[mode_lib->mp.qos_param_index].maximum_latency_when_non_urgent_uclk_cycles
/ mode_lib->mp.uclk_freq_mhz * (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.umc_max_latency_margin / 100.0)
+ mode_lib->soc.qos_parameters.qos_params.dcn4.mall_overhead_fclk_cycles / mode_lib->mp.FabricClock
+ mode_lib->soc.qos_parameters.qos_params.dcn4.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->mp.FabricClock
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4.fabric_max_transport_latency_margin / 100.0);
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4) {
if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024
/ mode_lib->mp.non_urg_bandwidth_required[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= out->informative.qos.max_non_urgent_latency_us) {
out->informative.misc.ROBUrgencyAvoidance = true;
} else {
out->informative.misc.ROBUrgencyAvoidance = false;
}
} else {
out->informative.misc.ROBUrgencyAvoidance = true;
}
}

109
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h
View File

@ -73,7 +73,6 @@ struct dml2_core_ip_params {
unsigned int subvp_swath_height_margin_lines;
unsigned int subvp_fw_processing_delay_us;
unsigned int subvp_pstate_allow_width_us;
double max_vactive_det_fill_delay_us;
// MRQ
bool dcn_mrq_present;
@ -207,6 +206,7 @@ struct dml2_core_internal_mode_support_info {
bool ScaleRatioAndTapsSupport;
bool SourceFormatPixelAndScanSupport;
bool P2IWith420;
bool DSCSlicesODMModeSupported;
bool DSCOnlyIfNecessaryWithBPP;
bool DSC422NativeNotSupported;
bool LinkRateDoesNotMatchDPVersion;
@ -238,7 +238,6 @@ struct dml2_core_internal_mode_support_info {
bool LinkCapacitySupport;
bool ROBSupport;
bool ROBUrgencyAvoidance;
bool OutstandingRequestsSupport;
bool OutstandingRequestsUrgencyAvoidance;
@ -301,6 +300,7 @@ struct dml2_core_internal_mode_support_info {
double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
@ -308,7 +308,6 @@ struct dml2_core_internal_mode_support_info {
bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
double max_non_urgent_latency_us;
double max_urgent_latency_us;
double avg_non_urgent_latency_us;
double avg_urgent_latency_us;
@ -480,6 +479,10 @@ struct dml2_core_internal_mode_support {
double meta_row_bw[DML2_MAX_PLANES];
unsigned int meta_row_bytes[DML2_MAX_PLANES];
double dpte_row_bw[DML2_MAX_PLANES];
double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
// Something that should be feedback to caller
enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];
@ -503,6 +506,7 @@ struct dml2_core_internal_mode_support {
double VActiveLatencyHidingMargin[DML2_MAX_PLANES];
double VActiveLatencyHidingUs[DML2_MAX_PLANES];
unsigned int MaxVStartupLines[DML2_MAX_PLANES];
double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES];
unsigned int num_mcaches_l[DML2_MAX_PLANES];
unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];
@ -557,6 +561,8 @@ struct dml2_core_internal_mode_program {
unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES];
double SurfaceReadBandwidthLuma[DML2_MAX_PLANES];
double SurfaceReadBandwidthChroma[DML2_MAX_PLANES];
double excess_vactive_fill_bw_l[DML2_MAX_PLANES];
double excess_vactive_fill_bw_c[DML2_MAX_PLANES];
unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES];
unsigned int vm_bytes[DML2_MAX_PLANES];
@ -798,6 +804,7 @@ struct dml2_core_internal_mode_program {
double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor
double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor
double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw
double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip
double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor
double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
@ -853,8 +860,12 @@ struct dml2_core_calcs_mode_support_locals {
unsigned int meta_row_height_luma[DML2_MAX_PLANES];
unsigned int meta_row_height_chroma[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
bool dummy_boolean[3];
bool dummy_boolean[2];
unsigned int dummy_integer[3];
unsigned int dummy_integer_array[36][DML2_MAX_PLANES];
enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];
@ -863,6 +874,7 @@ struct dml2_core_calcs_mode_support_locals {
double dummy_single_array[DML2_MAX_PLANES];
struct dml2_core_internal_watermarks dummy_watermark;
double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
unsigned int MaximumVStartup[DML2_MAX_PLANES];
unsigned int DSTYAfterScaler[DML2_MAX_PLANES];
@ -934,6 +946,10 @@ struct dml2_core_calcs_mode_support_locals {
unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];
unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];
unsigned int cursor_bytes[DML2_MAX_PLANES];
bool stream_visited[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
};
struct dml2_core_calcs_mode_programming_locals {
@ -946,6 +962,8 @@ struct dml2_core_calcs_mode_programming_locals {
double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];
unsigned int dummy_integer_array[2][DML2_MAX_PLANES];
enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES];
double dummy_single_array[2][DML2_MAX_PLANES];
@ -984,6 +1002,11 @@ struct dml2_core_calcs_mode_programming_locals {
unsigned int full_swath_bytes_l[DML2_MAX_PLANES];
unsigned int full_swath_bytes_c[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];
unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];
unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];
unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];
unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];
unsigned int tdlut_row_bytes[DML2_MAX_PLANES];
@ -1004,6 +1027,9 @@ struct dml2_core_calcs_mode_programming_locals {
double Tvm_trips_flip_rounded[DML2_MAX_PLANES];
double Tr0_trips_flip_rounded[DML2_MAX_PLANES];
unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];
unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];
};
struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals {
@ -1113,6 +1139,8 @@ struct dml2_core_calcs_CalculateVMRowAndSwath_params {
unsigned int *MaxNumSwathC;
double *dpte_row_bw;
unsigned int *PixelPTEBytesPerRow;
unsigned int *dpte_row_bytes_per_row_l;
unsigned int *dpte_row_bytes_per_row_c;
unsigned int *vm_bytes;
bool *use_one_row_for_frame;
bool *use_one_row_for_frame_flip;
@ -1134,6 +1162,8 @@ struct dml2_core_calcs_CalculateVMRowAndSwath_params {
unsigned int *meta_pte_bytes_per_frame_ub_c;
double *meta_row_bw;
unsigned int *meta_row_bytes;
unsigned int *meta_row_bytes_per_row_ub_l;
unsigned int *meta_row_bytes_per_row_ub_c;
};
struct dml2_core_calcs_CalculatePrefetchSchedule_locals {
@ -1307,6 +1337,7 @@ struct dml2_core_shared_get_urgent_bandwidth_required_locals {
struct dml2_core_shared_calculate_peak_bandwidth_required_locals {
double unity_array[DML2_MAX_PLANES];
double zero_array[DML2_MAX_PLANES];
double surface_dummy_bw[DML2_MAX_PLANES];
};
struct dml2_core_shared_CalculateFlipSchedule_locals {
@ -1588,6 +1619,7 @@ struct dml2_core_calcs_CalculateStutterEfficiency_locals {
double TotalZeroSizeCompressedReadBandwidth;
double AverageDCCZeroSizeFraction;
double AverageZeroSizeCompressionRate;
bool stream_visited[DML2_MAX_PLANES];
};
struct dml2_core_calcs_CalculateStutterEfficiency_params {
@ -1870,6 +1902,73 @@ struct dml2_core_calcs_calculate_tdlut_setting_params {
unsigned int *tdlut_bytes_per_group;
};
struct dml2_core_calcs_calculate_peak_bandwidth_required_params {
// output
double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max];
double (*urg_bandwidth_required)[dml2_core_internal_bw_max];
double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max];
double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max];
double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];
// input
const struct dml2_display_cfg *display_cfg;
bool inc_flip_bw;
unsigned int num_active_planes;
unsigned int *num_of_dpp;
double *dcc_dram_bw_nom_overhead_factor_p0;
double *dcc_dram_bw_nom_overhead_factor_p1;
double *dcc_dram_bw_pref_overhead_factor_p0;
double *dcc_dram_bw_pref_overhead_factor_p1;
double *mall_prefetch_sdp_overhead_factor;
double *mall_prefetch_dram_overhead_factor;
double *surface_read_bandwidth_l;
double *surface_read_bandwidth_c;
double *prefetch_bandwidth_l;
double *prefetch_bandwidth_c;
double *excess_vactive_fill_bw_l;
double *excess_vactive_fill_bw_c;
double *cursor_bw;
double *dpte_row_bw;
double *meta_row_bw;
double *prefetch_cursor_bw;
double *prefetch_vmrow_bw;
double *flip_bw;
double *urgent_burst_factor_l;
double *urgent_burst_factor_c;
double *urgent_burst_factor_cursor;
double *urgent_burst_factor_prefetch_l;
double *urgent_burst_factor_prefetch_c;
double *urgent_burst_factor_prefetch_cursor;
};
struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params {
/* inputs */
const struct dml2_display_cfg *display_cfg;
bool mrq_present;
unsigned int num_active_planes;
unsigned int *num_of_dpp;
unsigned int *meta_row_height_l;
unsigned int *meta_row_height_c;
unsigned int *meta_row_bytes_per_row_ub_l;
unsigned int *meta_row_bytes_per_row_ub_c;
unsigned int *dpte_row_height_l;
unsigned int *dpte_row_height_c;
unsigned int *dpte_bytes_per_row_l;
unsigned int *dpte_bytes_per_row_c;
unsigned int *byte_per_pix_l;
unsigned int *byte_per_pix_c;
unsigned int *swath_width_l;
unsigned int *swath_width_c;
unsigned int *swath_height_l;
unsigned int *swath_height_c;
double latency_to_hide_us;
/* outputs */
unsigned int *bytes_required_l;
unsigned int *bytes_required_c;
};
// A list of overridable function pointers in the core
// shared calculation library.
struct dml2_core_shared_calculation_funcs {
@ -1903,6 +2002,8 @@ struct dml2_core_internal_scratch {
struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params;
struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals;
struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params;
struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params;
struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params;
};
//struct dml2_svp_mode_override;

96
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
View File

@ -58,7 +58,10 @@ static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dp
min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100);
min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config);
min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100);
if (in_out->display_cfg->display_config.hostvm_enable)
min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100);
else
min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100);
min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg;
@ -226,13 +229,9 @@ static bool round_up_to_next_dpm(unsigned long *clock_value, const struct dml2_c
return round_up_and_copy_to_next_dpm(*clock_value, clock_value, clock_table);
}
static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mode_support_result, struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
static bool map_soc_min_clocks_to_dpm_fine_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
{
bool result;
unsigned int i;
if (!state_table || !display_cfg)
return false;
result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4.active.dcfclk_khz, &state_table->dcfclk);
if (result)
@ -254,6 +253,77 @@ static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mo
if (result)
result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4.idle.uclk_khz, &state_table->uclk);
return result;
}
static bool map_soc_min_clocks_to_dpm_coarse_grained(struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
{
bool result;
int index;
result = false;
for (index = 0; index < state_table->uclk.num_clk_values; index++) {
if (display_cfg->min_clocks.dcn4.active.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] &&
display_cfg->min_clocks.dcn4.active.fclk_khz <= state_table->fclk.clk_values_khz[index] &&
display_cfg->min_clocks.dcn4.active.uclk_khz <= state_table->uclk.clk_values_khz[index]) {
display_cfg->min_clocks.dcn4.active.dcfclk_khz = state_table->dcfclk.clk_values_khz[index];
display_cfg->min_clocks.dcn4.active.fclk_khz = state_table->fclk.clk_values_khz[index];
display_cfg->min_clocks.dcn4.active.uclk_khz = state_table->uclk.clk_values_khz[index];
result = true;
break;
}
}
if (result) {
result = false;
for (index = 0; index < state_table->uclk.num_clk_values; index++) {
if (display_cfg->min_clocks.dcn4.idle.dcfclk_khz <= state_table->dcfclk.clk_values_khz[index] &&
display_cfg->min_clocks.dcn4.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] &&
display_cfg->min_clocks.dcn4.idle.uclk_khz <= state_table->uclk.clk_values_khz[index]) {
display_cfg->min_clocks.dcn4.idle.dcfclk_khz = state_table->dcfclk.clk_values_khz[index];
display_cfg->min_clocks.dcn4.idle.fclk_khz = state_table->fclk.clk_values_khz[index];
display_cfg->min_clocks.dcn4.idle.uclk_khz = state_table->uclk.clk_values_khz[index];
result = true;
break;
}
}
}
// SVP is not supported on any coarse grained SoCs
display_cfg->min_clocks.dcn4.svp_prefetch.dcfclk_khz = 0;
display_cfg->min_clocks.dcn4.svp_prefetch.fclk_khz = 0;
display_cfg->min_clocks.dcn4.svp_prefetch.uclk_khz = 0;
return result;
}
static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mode_support_result, struct dml2_display_cfg_programming *display_cfg, const struct dml2_soc_state_table *state_table)
{
bool result = false;
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_identical = false;
unsigned int i;
if (!state_table || !display_cfg)
return false;
if (state_table->dcfclk.num_clk_values == 2) {
dcfclk_fine_grained = true;
}
if (state_table->fclk.num_clk_values == 2) {
fclk_fine_grained = true;
}
if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values &&
state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) {
clock_state_count_identical = true;
}
if (dcfclk_fine_grained || fclk_fine_grained || !clock_state_count_identical)
result = map_soc_min_clocks_to_dpm_fine_grained(display_cfg, state_table);
else
result = map_soc_min_clocks_to_dpm_coarse_grained(display_cfg, state_table);
if (result)
result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4.dispclk_khz, &state_table->dispclk);
@ -285,11 +355,11 @@ static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *mo
static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *display_config, int mask)
{
unsigned int i;
unsigned char i;
bool identical = true;
bool contains_drr = false;
unsigned int remap_array[DML2_MAX_PLANES];
unsigned int remap_array_size = 0;
unsigned char remap_array[DML2_MAX_PLANES];
unsigned char remap_array_size = 0;
// Create a remap array to enable simple iteration through only masked stream indicies
for (i = 0; i < display_config->num_streams; i++) {
@ -324,10 +394,10 @@ static bool are_timings_trivially_synchronizable(struct dml2_display_cfg *displa
static int find_smallest_idle_time_in_vblank_us(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out, int mask)
{
unsigned int i;
unsigned char i;
int min_idle_us = 0;
unsigned int remap_array[DML2_MAX_PLANES];
unsigned int remap_array_size = 0;
unsigned char remap_array[DML2_MAX_PLANES];
unsigned char remap_array_size = 0;
const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result;
// Create a remap array to enable simple iteration through only masked stream indicies
@ -468,7 +538,7 @@ static bool map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_o
calculate_svp_prefetch_minimums(in_out);
calculate_idle_minimums(in_out);
// In DCN4, there's no support for FCLK or DCFCLK DPM change before SVP prefetch starts, therefore
// In NV4, there's no support for FCLK or DCFCLK DPM change before SVP prefetch starts, therefore
// active minimums must be boosted to prefetch minimums
if (in_out->programming->min_clocks.dcn4.svp_prefetch.uclk_khz > in_out->programming->min_clocks.dcn4.active.uclk_khz)
in_out->programming->min_clocks.dcn4.active.uclk_khz = in_out->programming->min_clocks.dcn4.svp_prefetch.uclk_khz;

1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
View File

@ -39,6 +39,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance
break;
case dml2_project_dcn4x_stage2_auto_drr_svp:
out->map_mode_to_soc_dpm = &dpmm_dcn4_map_mode_to_soc_dpm;
out->map_watermarks = &dpmm_dcn4_map_watermarks;
result = true;
break;
case dml2_project_invalid:

101
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c
View File

@ -37,52 +37,28 @@ static unsigned long round_up_to_quantized_values(unsigned long value, const uns
return 0;
}
static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
static bool build_min_clk_table_fine_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
{
bool dcfclk_fine_grained = false, fclk_fine_grained = false;
int i;
unsigned int j;
bool dcfclk_fine_grained = false, fclk_fine_grained = false;
unsigned long min_dcfclk_khz = 0, max_dcfclk_khz = 0;
unsigned long min_fclk_khz = 0, max_fclk_khz = 0;
unsigned long min_dcfclk_khz = 0;
unsigned long min_fclk_khz = 0;
unsigned long prev_100, cur_50;
if (!soc_bb || !min_table)
return false;
if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2)
return false;
if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE)
return false;
min_table->fixed_clocks_khz.amclk = 0;
min_table->fixed_clocks_khz.dprefclk = soc_bb->dprefclk_mhz * 1000;
min_table->fixed_clocks_khz.pcierefclk = soc_bb->pcie_refclk_mhz * 1000;
min_table->fixed_clocks_khz.dchubrefclk = soc_bb->dchub_refclk_mhz * 1000;
min_table->fixed_clocks_khz.xtalclk = soc_bb->xtalclk_mhz * 1000;
if (soc_bb->clk_table.dcfclk.num_clk_values == 2) {
dcfclk_fine_grained = true;
}
max_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values - 1];
min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[0];
if (soc_bb->clk_table.fclk.num_clk_values == 2) {
fclk_fine_grained = true;
}
max_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values - 1];
min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[0];
min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0];
min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dispclk.num_clk_values - 1];
min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppclk.num_clk_values - 1];
min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dscclk.num_clk_values - 1];
min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1];
min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values - 1];
min_table->max_clocks_khz.dcfclk = max_dcfclk_khz;
min_table->max_clocks_khz.fclk = max_fclk_khz;
// First calculate the table for "balanced" bandwidths across UCLK/FCLK
for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) {
min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config);
@ -154,3 +130,66 @@ static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_
return true;
}
static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
{
int i;
for (i = 0; i < soc_bb->clk_table.uclk.num_clk_values; i++) {
min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config);
min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i];
min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i];
}
min_table->dram_bw_table.num_entries = soc_bb->clk_table.uclk.num_clk_values;
return true;
}
static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table)
{
bool result;
bool dcfclk_fine_grained = false, fclk_fine_grained = false, clock_state_count_equal = false;
if (!soc_bb || !min_table)
return false;
if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2)
return false;
if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE)
return false;
if (soc_bb->clk_table.dcfclk.num_clk_values == 2) {
dcfclk_fine_grained = true;
}
if (soc_bb->clk_table.fclk.num_clk_values == 2) {
fclk_fine_grained = true;
}
if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values &&
soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values)
clock_state_count_equal = true;
min_table->fixed_clocks_khz.amclk = 0;
min_table->fixed_clocks_khz.dprefclk = soc_bb->dprefclk_mhz * 1000;
min_table->fixed_clocks_khz.pcierefclk = soc_bb->pcie_refclk_mhz * 1000;
min_table->fixed_clocks_khz.dchubrefclk = soc_bb->dchub_refclk_mhz * 1000;
min_table->fixed_clocks_khz.xtalclk = soc_bb->xtalclk_mhz * 1000;
min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dispclk.num_clk_values - 1];
min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppclk.num_clk_values - 1];
min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dscclk.num_clk_values - 1];
min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1];
min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values - 1];
min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values - 1];
min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values - 1];
if (dcfclk_fine_grained || fclk_fine_grained || !clock_state_count_equal)
result = build_min_clk_table_fine_grained(soc_bb, min_table);
else
result = build_min_clk_table_coarse_grained(soc_bb, min_table);
return result;
}

2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h
View File

@ -11,4 +11,4 @@
bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out);
bool mcg_dcn4_unit_test(void);
#endif
#endif

29
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c
View File

@ -22,6 +22,23 @@ static void sort(double *list_a, int list_a_size)
}
}
static double get_max_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index)
{
struct dml2_plane_parameters *plane_descriptor;
long max_reserved_time_ns = 0;
for (unsigned int i = 0; i < config->display_config.num_planes; i++) {
plane_descriptor = &config->display_config.plane_descriptors[i];
if (plane_descriptor->stream_index == stream_index)
if (plane_descriptor->overrides.reserved_vblank_time_ns > max_reserved_time_ns)
max_reserved_time_ns = plane_descriptor->overrides.reserved_vblank_time_ns;
}
return (max_reserved_time_ns / 1000.0);
}
static void set_reserved_time_on_all_planes_with_stream_index(struct display_configuation_with_meta *config, unsigned int stream_index, double reserved_time_us)
{
struct dml2_plane_parameters *plane_descriptor;
@ -183,11 +200,11 @@ static int count_planes_with_stream_index(const struct dml2_display_cfg *display
static bool are_timings_trivially_synchronizable(struct display_configuation_with_meta *display_config, int mask)
{
unsigned int i;
unsigned char i;
bool identical = true;
bool contains_drr = false;
unsigned int remap_array[DML2_MAX_PLANES];
unsigned int remap_array_size = 0;
unsigned char remap_array[DML2_MAX_PLANES];
unsigned char remap_array_size = 0;
// Create a remap array to enable simple iteration through only masked stream indicies
for (i = 0; i < display_config->display_config.num_streams; i++) {
@ -227,7 +244,7 @@ bool pmo_dcn3_initialize(struct dml2_pmo_initialize_in_out *in_out)
pmo->ip_caps = in_out->ip_caps;
pmo->mpc_combine_limit = 2;
pmo->odm_combine_limit = 4;
pmo->min_clock_table_size = in_out->min_clock_table_size;
pmo->mcg_clock_table_size = in_out->mcg_clock_table_size;
pmo->options = in_out->options;
@ -520,7 +537,7 @@ bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in
state->performed = true;
state->min_clk_index_for_latency = in_out->base_display_config->stage1.min_clk_index_for_latency;
pmo->scratch.pmo_dcn3.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
pmo->scratch.pmo_dcn3.max_latency_index = pmo->min_clock_table_size;
pmo->scratch.pmo_dcn3.max_latency_index = pmo->mcg_clock_table_size - 1;
pmo->scratch.pmo_dcn3.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
pmo->scratch.pmo_dcn3.stream_mask = 0xF;
@ -578,6 +595,8 @@ bool pmo_dcn3_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in
in_out->instance->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us);
*/
min_reserved_vblank_time = get_max_reserved_time_on_all_planes_with_stream_index(in_out->base_display_config, stream_index);
// Insert the absolute minimum into the array
candidate_count = 1;
pmo->scratch.pmo_dcn3.reserved_time_candidates[stream_index][0] = min_reserved_vblank_time;

38
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4.c
View File

@ -284,7 +284,7 @@ bool pmo_dcn4_initialize(struct dml2_pmo_initialize_in_out *in_out)
pmo->ip_caps = in_out->ip_caps;
pmo->mpc_combine_limit = 2;
pmo->odm_combine_limit = 4;
pmo->min_clock_table_size = in_out->min_clock_table_size;
pmo->mcg_clock_table_size = in_out->mcg_clock_table_size;
pmo->fams_params.v1.subvp.fw_processing_delay_us = 10;
pmo->fams_params.v1.subvp.prefetch_end_to_mall_start_us = 50;
@ -499,11 +499,11 @@ bool pmo_dcn4_optimize_for_vmin(struct dml2_pmo_optimize_for_vmin_in_out *in_out
static bool are_timings_trivially_synchronizable(const struct display_configuation_with_meta *display_config, int mask)
{
unsigned int i;
unsigned char i;
bool identical = true;
bool contains_drr = false;
unsigned int remap_array[DML2_MAX_PLANES];
unsigned int remap_array_size = 0;
unsigned char remap_array[DML2_MAX_PLANES];
unsigned char remap_array_size = 0;
// Create a remap array to enable simple iteration through only masked stream indicies
for (i = 0; i < display_config->display_config.num_streams; i++) {
@ -603,7 +603,7 @@ static bool all_planes_match_strategy(const struct display_configuation_with_met
}
static bool subvp_subvp_schedulable(struct dml2_pmo_instance *pmo, const struct display_configuation_with_meta *display_cfg,
unsigned int *svp_stream_indicies, int svp_stream_count)
unsigned char *svp_stream_indicies, char svp_stream_count)
{
struct dml2_pmo_scratch *s = &pmo->scratch;
int i;
@ -669,10 +669,10 @@ static bool validate_svp_cofunctionality(struct dml2_pmo_instance *pmo,
const struct display_configuation_with_meta *display_cfg, int svp_stream_mask)
{
bool result = false;
unsigned int stream_index;
unsigned char stream_index;
unsigned int svp_stream_indicies[2] = { 0 };
unsigned int svp_stream_count = 0;
unsigned char svp_stream_indicies[2] = { 0 };
unsigned char svp_stream_count = 0;
// Find the SVP streams, store only the first 2, but count all of them
for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) {
@ -696,7 +696,7 @@ static bool validate_svp_cofunctionality(struct dml2_pmo_instance *pmo,
static bool validate_drr_cofunctionality(struct dml2_pmo_instance *pmo,
const struct display_configuation_with_meta *display_cfg, int drr_stream_mask)
{
unsigned int stream_index;
unsigned char stream_index;
int drr_stream_count = 0;
// Find the SVP streams and count all of them
@ -712,7 +712,7 @@ static bool validate_drr_cofunctionality(struct dml2_pmo_instance *pmo,
static bool validate_svp_drr_cofunctionality(struct dml2_pmo_instance *pmo,
const struct display_configuation_with_meta *display_cfg, int svp_stream_mask, int drr_stream_mask)
{
unsigned int stream_index;
unsigned char stream_index;
int drr_stream_count = 0;
int svp_stream_count = 0;
@ -781,7 +781,7 @@ static bool validate_svp_drr_cofunctionality(struct dml2_pmo_instance *pmo,
static bool validate_svp_vblank_cofunctionality(struct dml2_pmo_instance *pmo,
const struct display_configuation_with_meta *display_cfg, int svp_stream_mask, int vblank_stream_mask)
{
unsigned int stream_index;
unsigned char stream_index;
int vblank_stream_count = 0;
int svp_stream_count = 0;
@ -853,7 +853,7 @@ static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_ins
{
struct dml2_pmo_scratch *s = &pmo->scratch;
unsigned int stream_index = 0;
unsigned char stream_index = 0;
unsigned int svp_count = 0;
unsigned int svp_stream_mask = 0;
@ -967,7 +967,7 @@ bool pmo_dcn4_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in
memset(s, 0, sizeof(struct dml2_pmo_scratch));
pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
pmo->scratch.pmo_dcn4.max_latency_index = pmo->min_clock_table_size;
pmo->scratch.pmo_dcn4.max_latency_index = pmo->mcg_clock_table_size - 1;
pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
// First build the stream plane mask (array of bitfields indexed by stream, indicating plane mapping)
@ -1071,7 +1071,7 @@ static void reset_display_configuration(struct display_configuation_with_meta *d
static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
struct dml2_plane_parameters *plane;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1088,7 +1088,7 @@ static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *
static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
int stream_index = -1;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1110,7 +1110,7 @@ static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *
static void setup_planes_for_vblank_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
struct dml2_plane_parameters *plane;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1127,7 +1127,7 @@ static void setup_planes_for_vblank_by_mask(struct display_configuation_with_met
static void setup_planes_for_vactive_by_mask(struct display_configuation_with_meta *display_config, int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
@ -1139,7 +1139,7 @@ static void setup_planes_for_vactive_by_mask(struct display_configuation_with_me
static bool setup_display_config(struct display_configuation_with_meta *display_config, struct dml2_pmo_scratch *scratch, int strategy_index)
{
bool success = true;
unsigned int stream_index;
unsigned char stream_index;
reset_display_configuration(display_config);
@ -1164,7 +1164,7 @@ static bool setup_display_config(struct display_configuation_with_meta *display_
static int get_minimum_reserved_time_us_for_planes(struct display_configuation_with_meta *display_config, int plane_mask)
{
int min_time_us = 0xFFFFFF;
unsigned int plane_index = 0;
unsigned char plane_index = 0;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {

173
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
View File

@ -29,8 +29,6 @@
#include "lib_float_math.h"
#include "dml2_pmo_dcn4_fams2.h"
#define PMO_DCN4_MIN_TIME_TO_DISALLOW_MS 0.0
static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding
static const enum dml2_pmo_pstate_strategy base_strategy_list_1_display[][PMO_DCN4_MAX_DISPLAYS] = {
@ -318,7 +316,7 @@ static enum dml2_pmo_pstate_strategy convert_strategy_to_drr_variant(const enum
case dml2_pmo_pstate_strategy_fw_drr:
case dml2_pmo_pstate_strategy_reserved_hw:
case dml2_pmo_pstate_strategy_reserved_fw:
case dml2_pmo_pstate_strategy_reserved_fw_drr_fixed:
case dml2_pmo_pstate_strategy_reserved_fw_drr_clamped:
case dml2_pmo_pstate_strategy_reserved_fw_drr_var:
case dml2_pmo_pstate_strategy_na:
default:
@ -492,13 +490,11 @@ static void expand_base_strategies(
expand_base_strategy(pmo, base_strategies_list[i], stream_count);
}
if (stream_count > 1) {
/* expand base strategies to DRR variants */
num_pre_variant_strategies = get_num_expanded_strategies(&pmo->init_data, stream_count);
expanded_strategy_list = get_expanded_strategy_list(&pmo->init_data, stream_count);
for (i = 0; i < num_pre_variant_strategies; i++) {
expand_variant_strategy(pmo, expanded_strategy_list[i], stream_count);
}
/* expand base strategies to DRR variants */
num_pre_variant_strategies = get_num_expanded_strategies(&pmo->init_data, stream_count);
expanded_strategy_list = get_expanded_strategy_list(&pmo->init_data, stream_count);
for (i = 0; i < num_pre_variant_strategies; i++) {
expand_variant_strategy(pmo, expanded_strategy_list[i], stream_count);
}
/* add back all DRR */
@ -514,7 +510,7 @@ bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out)
pmo->ip_caps = in_out->ip_caps;
pmo->mpc_combine_limit = 2;
pmo->odm_combine_limit = 4;
pmo->min_clock_table_size = in_out->min_clock_table_size;
pmo->mcg_clock_table_size = in_out->mcg_clock_table_size;
pmo->fams_params.v2.subvp.refresh_rate_limit_max = 175;
pmo->fams_params.v2.subvp.refresh_rate_limit_min = 0;
@ -887,7 +883,7 @@ static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo,
stream_descriptor = &display_config->display_config.stream_descriptors[i];
stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[i];
if (!stream_descriptor->timing.drr_config.enabled)
if (!stream_descriptor->timing.drr_config.enabled || stream_descriptor->overrides.disable_fams2_drr)
return false;
/* cannot support required vtotal */
@ -920,7 +916,7 @@ static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo,
const struct dml2_plane_parameters *plane_descriptor;
const struct dml2_fams2_meta *stream_fams2_meta;
unsigned int microschedule_vlines;
unsigned int i;
unsigned char i;
unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 };
@ -1016,7 +1012,7 @@ static void build_method_scheduling_params(
struct dml2_fams2_meta *stream_fams2_meta)
{
stream_method_fams2_meta->allow_time_us =
(double)(stream_method_fams2_meta->allow_end_otg_vline - stream_method_fams2_meta->allow_start_otg_vline) *
(double)((int)stream_method_fams2_meta->allow_end_otg_vline - (int)stream_method_fams2_meta->allow_start_otg_vline) *
stream_fams2_meta->otg_vline_time_us;
if (stream_method_fams2_meta->allow_time_us >= stream_method_fams2_meta->period_us) {
/* when allow wave overlaps an entire frame, it is always schedulable (DRR can do this)*/
@ -1052,7 +1048,7 @@ static struct dml2_fams2_per_method_common_meta *get_per_method_common_meta(
break;
case dml2_pmo_pstate_strategy_reserved_hw:
case dml2_pmo_pstate_strategy_reserved_fw:
case dml2_pmo_pstate_strategy_reserved_fw_drr_fixed:
case dml2_pmo_pstate_strategy_reserved_fw_drr_clamped:
case dml2_pmo_pstate_strategy_reserved_fw_drr_var:
case dml2_pmo_pstate_strategy_na:
default:
@ -1113,7 +1109,8 @@ static bool is_timing_group_schedulable(
/* calculate the rest of the meta */
build_method_scheduling_params(group_fams2_meta, &pmo->scratch.pmo_dcn4.stream_fams2_meta[base_stream_idx]);
return true;
return group_fams2_meta->allow_time_us > 0.0 &&
group_fams2_meta->disallow_time_us < pmo->ip_caps->fams2.max_allow_delay_us;
}
static bool is_config_schedulable(
@ -1125,14 +1122,15 @@ static bool is_config_schedulable(
bool schedulable;
struct dml2_pmo_scratch *s = &pmo->scratch;
double max_allow_delay_us = 0.0;
memset(s->pmo_dcn4.group_common_fams2_meta, 0, sizeof(s->pmo_dcn4.group_common_fams2_meta));
memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES);
/* search for a general solution to the schedule */
/* STAGE 0: Early return for special cases */
if (display_cfg->display_config.num_streams <= 1) {
/* single stream is always schedulable */
if (display_cfg->display_config.num_streams == 0) {
return true;
}
@ -1146,6 +1144,7 @@ static bool is_config_schedulable(
schedulable = false;
break;
}
max_allow_delay_us += s->pmo_dcn4.group_common_fams2_meta[i].disallow_time_us;
}
if ((schedulable && s->pmo_dcn4.num_timing_groups <= 1) || !schedulable) {
@ -1211,7 +1210,7 @@ static bool is_config_schedulable(
}
}
if (schedulable) {
if (schedulable && max_allow_delay_us < pmo->ip_caps->fams2.max_allow_delay_us) {
return true;
}
@ -1243,6 +1242,7 @@ static bool is_config_schedulable(
for (i = 0; i < s->pmo_dcn4.num_timing_groups - 1; i++) {
unsigned int sorted_i = s->pmo_dcn4.sorted_group_gtl_period_index[i];
unsigned int sorted_ip1 = s->pmo_dcn4.sorted_group_gtl_period_index[i + 1];
if (s->pmo_dcn4.group_common_fams2_meta[sorted_i].allow_time_us < s->pmo_dcn4.group_common_fams2_meta[sorted_ip1].period_us ||
s->pmo_dcn4.group_is_drr_enabled[sorted_ip1]) {
schedulable = false;
@ -1250,38 +1250,34 @@ static bool is_config_schedulable(
}
}
/* STAGE 4: For similar frequencies, and when using HW exclusive modes, check disallow alignments are within allowed threshold */
if (schedulable && max_allow_delay_us < pmo->ip_caps->fams2.max_allow_delay_us) {
return true;
}
/* STAGE 4: When using HW exclusive modes, check disallow alignments are within allowed threshold */
if (s->pmo_dcn4.num_timing_groups == 2 &&
!is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, per_stream_pstate_strategy[0]) &&
!is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, per_stream_pstate_strategy[1])) {
double period_delta = s->pmo_dcn4.group_common_fams2_meta[0].period_us - s->pmo_dcn4.group_common_fams2_meta[1].period_us;
double period_ratio;
double max_shift_us;
double shift_per_period;
/* default period_0 > period_1 */
unsigned int lrg_idx = 0;
unsigned int sml_idx = 1;
if (period_delta < 0.0) {
if (s->pmo_dcn4.group_common_fams2_meta[0].period_us < s->pmo_dcn4.group_common_fams2_meta[1].period_us) {
/* period_0 < period_1 */
lrg_idx = 1;
sml_idx = 0;
period_delta = math_fabs(period_delta);
}
period_ratio = s->pmo_dcn4.group_common_fams2_meta[lrg_idx].period_us / s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us;
shift_per_period = s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us * (period_ratio - math_floor(period_ratio));
max_shift_us = s->pmo_dcn4.group_common_fams2_meta[lrg_idx].disallow_time_us - s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us;
max_allow_delay_us = max_shift_us / shift_per_period * s->pmo_dcn4.group_common_fams2_meta[lrg_idx].period_us;
if (s->pmo_dcn4.group_common_fams2_meta[lrg_idx].disallow_time_us >= s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us) {
double time_until_disallow_us = (s->pmo_dcn4.group_common_fams2_meta[lrg_idx].allow_time_us +
s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us) /
period_delta *
s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us;
double time_until_allow_us = (s->pmo_dcn4.group_common_fams2_meta[lrg_idx].disallow_time_us -
s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us) /
period_delta *
s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us;
if (time_until_disallow_us > PMO_DCN4_MIN_TIME_TO_DISALLOW_MS &&
time_until_allow_us < pmo->ip_caps->fams2.max_allow_delay_us) {
schedulable = true;
}
} else {
/* if the allow is not maskable, it is always schedulable within a frame */
if (shift_per_period > 0.0 &&
shift_per_period < s->pmo_dcn4.group_common_fams2_meta[lrg_idx].allow_time_us + s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us &&
max_allow_delay_us < pmo->ip_caps->fams2.max_allow_delay_us) {
schedulable = true;
}
}
@ -1308,7 +1304,7 @@ static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,
is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, stream_pstate_strategy) &&
stream_descriptor->timing.drr_config.enabled &&
stream_descriptor->timing.drr_config.drr_active_variable) {
/* DRR is variable, fw exclusive methods require DRR to be fixed */
/* DRR is variable, fw exclusive methods require DRR to be clamped */
strategy_matches_drr_requirements = false;
} else if (is_bit_set_in_bitfield(PMO_DRR_VAR_STRATEGY_MASK, stream_pstate_strategy) &&
pmo->options->disable_drr_var_when_var_active &&
@ -1322,10 +1318,9 @@ static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,
stream_descriptor->timing.drr_config.disallowed)) {
/* DRR variable strategies are disallowed due to settings or policy */
strategy_matches_drr_requirements = false;
} else if (is_bit_set_in_bitfield(PMO_DRR_FIXED_STRATEGY_MASK, stream_pstate_strategy) &&
(pmo->options->disable_drr_fixed ||
(stream_descriptor->timing.drr_config.enabled &&
stream_descriptor->timing.drr_config.drr_active_variable))) {
} else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_strategy) &&
(pmo->options->disable_drr_clamped ||
!stream_descriptor->timing.drr_config.enabled)) {
/* DRR fixed strategies are disallowed due to settings or policy */
strategy_matches_drr_requirements = false;
} else if (is_bit_set_in_bitfield(PMO_FW_STRATEGY_MASK, stream_pstate_strategy) &&
@ -1420,6 +1415,21 @@ static int get_vactive_pstate_margin(const struct display_configuation_with_meta
return min_vactive_margin_us;
}
static unsigned int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask)
{
unsigned char i;
unsigned int max_vactive_fill_us = 0;
for (i = 0; i < DML2_MAX_PLANES; i++) {
if (is_bit_set_in_bitfield(plane_mask, i)) {
if (display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us > max_vactive_fill_us)
max_vactive_fill_us = display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us;
}
}
return max_vactive_fill_us;
}
static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo,
struct display_configuation_with_meta *display_config,
int stream_index)
@ -1474,18 +1484,34 @@ static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo,
(unsigned int)math_ceil(ip_caps->fams2.min_allow_width_us / stream_fams2_meta->otg_vline_time_us);
/* this value should account for urgent latency */
stream_fams2_meta->dram_clk_change_blackout_otg_vlines =
(unsigned int)math_ceil(display_config->mode_support_result.cfg_support_info.clean_me_up.support_info.watermarks.DRAMClockChangeWatermark /
(unsigned int)math_ceil(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us /
stream_fams2_meta->otg_vline_time_us);
/* scheduling params should be built based on the worst case for allow_time:disallow_time */
/* vactive */
stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines =
(unsigned int)math_ceil(ip_caps->max_vactive_det_fill_delay_us / stream_fams2_meta->otg_vline_time_us);
stream_fams2_meta->method_vactive.common.allow_start_otg_vline =
if (display_config->display_config.num_streams == 1) {
/* for single stream, guarantee at least an instant of allow */
stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines = (unsigned int)math_floor(
math_max2(0.0,
timing->v_active - stream_fams2_meta->min_allow_width_otg_vlines - stream_fams2_meta->dram_clk_change_blackout_otg_vlines));
} else {
/* for multi stream, bound to a max fill time defined by IP caps */
stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines =
(unsigned int)math_floor((double)ip_caps->max_vactive_det_fill_delay_us / stream_fams2_meta->otg_vline_time_us);
}
stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us = stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines * stream_fams2_meta->otg_vline_time_us;
if (stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us > 0.0) {
stream_fams2_meta->method_vactive.common.allow_start_otg_vline =
timing->v_blank_end + stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines;
stream_fams2_meta->method_vactive.common.allow_end_otg_vline =
timing->v_blank_end + timing->v_active - stream_fams2_meta->dram_clk_change_blackout_otg_vlines;
stream_fams2_meta->method_vactive.common.allow_end_otg_vline =
timing->v_blank_end + timing->v_active -
stream_fams2_meta->dram_clk_change_blackout_otg_vlines;
} else {
stream_fams2_meta->method_vactive.common.allow_start_otg_vline = 0;
stream_fams2_meta->method_vactive.common.allow_end_otg_vline = 0;
}
stream_fams2_meta->method_vactive.common.period_us = stream_fams2_meta->nom_frame_time_us;
build_method_scheduling_params(&stream_fams2_meta->method_vactive.common, stream_fams2_meta);
@ -1583,7 +1609,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp
const struct dml2_plane_parameters *plane_descriptor;
const enum dml2_pmo_pstate_strategy(*strategy_list)[PMO_DCN4_MAX_DISPLAYS] = NULL;
unsigned int strategy_list_size = 0;
unsigned int plane_index, stream_index, i;
unsigned char plane_index, stream_index, i;
state->performed = true;
in_out->base_display_config->stage3.min_clk_index_for_latency = in_out->base_display_config->stage1.min_clk_index_for_latency;
@ -1594,7 +1620,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp
memset(s, 0, sizeof(struct dml2_pmo_scratch));
pmo->scratch.pmo_dcn4.min_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
pmo->scratch.pmo_dcn4.max_latency_index = pmo->min_clock_table_size;
pmo->scratch.pmo_dcn4.max_latency_index = pmo->mcg_clock_table_size;
pmo->scratch.pmo_dcn4.cur_latency_index = in_out->base_display_config->stage1.min_clk_index_for_latency;
// First build the stream plane mask (array of bitfields indexed by stream, indicating plane mapping)
@ -1636,16 +1662,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp
}
if (s->pmo_dcn4.num_pstate_candidates > 0) {
// There's this funny case...
// If the first entry in the candidate list is all vactive, then we can consider it "tested", so the current index is 0
// Otherwise the current index should be -1 because we run the optimization at least once
s->pmo_dcn4.cur_pstate_candidate = 0;
for (i = 0; i < display_config->display_config.num_streams; i++) {
if (s->pmo_dcn4.per_stream_pstate_strategy[0][i] != dml2_pmo_pstate_strategy_vactive) {
s->pmo_dcn4.cur_pstate_candidate = -1;
break;
}
}
s->pmo_dcn4.cur_pstate_candidate = -1;
return true;
} else {
return false;
@ -1685,7 +1702,7 @@ static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *
struct dml2_pmo_instance *pmo,
int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
struct dml2_plane_parameters *plane;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1706,7 +1723,7 @@ static void setup_planes_for_svp_by_mask(struct display_configuation_with_meta *
{
struct dml2_pmo_scratch *scratch = &pmo->scratch;
unsigned int plane_index;
unsigned char plane_index;
int stream_index = -1;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1750,7 +1767,7 @@ static void setup_planes_for_vblank_by_mask(struct display_configuation_with_met
struct dml2_pmo_instance *pmo,
int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
struct dml2_plane_parameters *plane;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
@ -1786,11 +1803,19 @@ static void setup_planes_for_vactive_by_mask(struct display_configuation_with_me
struct dml2_pmo_instance *pmo,
int plane_mask)
{
unsigned int plane_index;
unsigned char plane_index;
unsigned int stream_index;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
stream_index = display_config->display_config.plane_descriptors[plane_index].stream_index;
display_config->stage3.pstate_switch_modes[plane_index] = dml2_uclk_pstate_support_method_vactive;
if (!pmo->options->disable_vactive_det_fill_bw_pad) {
display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us =
(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);
}
}
}
}
@ -1800,10 +1825,18 @@ static void setup_planes_for_vactive_drr_by_mask(struct display_configuation_wit
int plane_mask)
{
unsigned char plane_index;
unsigned int stream_index;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
stream_index = display_config->display_config.plane_descriptors[plane_index].stream_index;
display_config->stage3.pstate_switch_modes[plane_index] = dml2_uclk_pstate_support_method_fw_vactive_drr;
if (!pmo->options->disable_vactive_det_fill_bw_pad) {
display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us =
(unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us);
}
}
}
}
@ -1846,7 +1879,7 @@ static bool setup_display_config(struct display_configuation_with_meta *display_
}
/* copy FAMS2 meta */
if (fams2_required) {
if (success) {
display_config->stage3.fams2_required = fams2_required;
memcpy(&display_config->stage3.stream_fams2_meta,
&scratch->pmo_dcn4.stream_fams2_meta,
@ -1859,7 +1892,7 @@ static bool setup_display_config(struct display_configuation_with_meta *display_
static int get_minimum_reserved_time_us_for_planes(struct display_configuation_with_meta *display_config, int plane_mask)
{
int min_time_us = 0xFFFFFF;
unsigned int plane_index = 0;
unsigned char plane_index = 0;
for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) {
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
@ -1888,10 +1921,12 @@ bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_supp
return false;
for (stream_index = 0; stream_index < in_out->base_display_config->display_config.num_streams; stream_index++) {
struct dml2_fams2_meta *stream_fams2_meta = &s->pmo_dcn4.stream_fams2_meta[stream_index];
if (s->pmo_dcn4.per_stream_pstate_strategy[s->pmo_dcn4.cur_pstate_candidate][stream_index] == dml2_pmo_pstate_strategy_vactive ||
s->pmo_dcn4.per_stream_pstate_strategy[s->pmo_dcn4.cur_pstate_candidate][stream_index] == dml2_pmo_pstate_strategy_fw_vactive_drr) {
if (get_vactive_pstate_margin(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) < (MIN_VACTIVE_MARGIN_PCT * in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us)) {
if (get_vactive_pstate_margin(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) < (MIN_VACTIVE_MARGIN_PCT * in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us) ||
get_vactive_det_fill_latency_delay_us(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) > stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us) {
p_state_supported = false;
break;
}

2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h
View File

@ -11,4 +11,4 @@
bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out);
#endif
#endif

16
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c
View File

@ -5,9 +5,7 @@
#include "lib_float_math.h"
#ifndef ASSERT
#define ASSERT(condition)
#endif
#define isNaN(number) ((number) != (number))
@ -132,9 +130,21 @@ float math_log2(float a)
return math_log(a, 2.0);
}
// approximate log2 value of a input
// - precise if the input pwr of 2, else the approximation will be an integer = floor(actual_log2)
unsigned int math_log2_approx(unsigned int a)
{
unsigned int log2_val = 0;
while (a > 1) {
a = a >> 1;
log2_val++;
}
return log2_val;
}
double math_round(double a)
{
const double round_pt = 0.5;
return math_floor(a + round_pt);
}
}

3
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h
View File

@ -20,6 +20,7 @@ float math_pow(float a, float exp);
double math_fabs(double a);
float math_log(float a, float b);
float math_log2(float a);
unsigned int math_log2_approx(unsigned int a);
double math_round(double a);
#endif
#endif

3
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top.c
View File

@ -72,7 +72,7 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
pmo_init_params.instance = &dml->pmo_instance;
pmo_init_params.soc_bb = &dml->soc_bbox;
pmo_init_params.ip_caps = &dml->ip_caps;
pmo_init_params.min_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries;
pmo_init_params.mcg_clock_table_size = dml->min_clk_table.dram_bw_table.num_entries;
pmo_init_params.options = &dml->pmo_options;
dml->pmo_instance.initialize(&pmo_init_params);
}
@ -123,6 +123,7 @@ bool dml2_check_mode_supported(struct dml2_check_mode_supported_in_out *in_out)
}
in_out->is_supported = mcache_success;
result = result && in_out->is_supported;
return result;
}

37
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top_mcache.c
View File

@ -319,6 +319,26 @@ bool dml2_top_mcache_validate_admissability(struct top_mcache_validate_admissabi
return all_pass;
}
static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs)
{
// Initialize all entries to special valid MCache ID and special valid split coordinate
per_plane_pipe_mcache_regs->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->main.p0.split_location = SPLIT_LOCATION_UNDEFINED;
per_plane_pipe_mcache_regs->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED;
per_plane_pipe_mcache_regs->main.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->main.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->main.p1.split_location = SPLIT_LOCATION_UNDEFINED;
per_plane_pipe_mcache_regs->mall.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->mall.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
per_plane_pipe_mcache_regs->mall.p1.split_location = SPLIT_LOCATION_UNDEFINED;
}
bool dml2_top_mcache_build_mcache_programming(struct dml2_build_mcache_programming_in_out *params)
{
bool success = true;
@ -333,22 +353,7 @@ bool dml2_top_mcache_build_mcache_programming(struct dml2_build_mcache_programmi
// Allocate storage for the mcache regs
params->per_plane_pipe_mcache_regs[config_index][pipe_index] = &params->mcache_regs_set[free_per_plane_reg_index++];
// First initialize all entries to special valid MCache ID and special valid split coordinate
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p0.split_location = SPLIT_LOCATION_UNDEFINED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->main.p1.split_location = SPLIT_LOCATION_UNDEFINED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.mcache_id_first = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.mcache_id_second = MCACHE_ID_UNASSIGNED;
params->per_plane_pipe_mcache_regs[config_index][pipe_index]->mall.p1.split_location = SPLIT_LOCATION_UNDEFINED;
reset_mcache_allocations(params->per_plane_pipe_mcache_regs[config_index][pipe_index]);
if (params->mcache_configurations[config_index].plane_descriptor->surface.dcc.enable) {
// P0 always enabled

2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml_top_mcache.h
View File

@ -21,4 +21,4 @@ bool dml2_top_mcache_build_mcache_programming(struct dml2_build_mcache_programmi
bool dml2_top_mcache_unit_test(void);
#endif
#endif

2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_debug.h
View File

@ -15,4 +15,4 @@
int dml2_printf(const char *format, ...);
void dml2_assert(int condition);
#endif
#endif

15
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h
View File

@ -146,10 +146,13 @@ struct core_plane_support_info {
int active_latency_hiding_us;
int mall_svp_size_requirement_ways;
int nominal_vblank_pstate_latency_hiding_us;
unsigned int dram_change_vactive_det_fill_delay_us;
};
struct core_stream_support_info {
unsigned int odms_used;
unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2)
/* FAMS2 SubVP support info */
unsigned int phantom_min_v_active;
unsigned int phantom_v_startup;
@ -270,6 +273,7 @@ struct dml2_fams2_meta {
double max_frame_time_us;
unsigned int dram_clk_change_blackout_otg_vlines;
struct {
double max_vactive_det_fill_delay_us;
unsigned int max_vactive_det_fill_delay_otg_vlines;
struct dml2_fams2_per_method_common_meta common;
} method_vactive;
@ -390,6 +394,7 @@ struct dml2_core_mode_programming_in_out {
* Outputs (also Input the clk freq are also from programming struct)
*/
struct dml2_display_cfg_programming *programming;
};
struct dml2_core_populate_informative_in_out {
@ -481,7 +486,7 @@ struct dml2_pmo_initialize_in_out {
struct dml2_soc_bb *soc_bb;
struct dml2_ip_capabilities *ip_caps;
struct dml2_pmo_options *options;
int min_clock_table_size;
int mcg_clock_table_size;
};
struct dml2_pmo_optimize_dcc_mcache_in_out {
@ -602,14 +607,14 @@ enum dml2_pmo_pstate_strategy {
dml2_pmo_pstate_strategy_fw_vactive_drr = 11,
dml2_pmo_pstate_strategy_fw_vblank_drr = 12,
dml2_pmo_pstate_strategy_fw_svp_drr = 13,
dml2_pmo_pstate_strategy_reserved_fw_drr_fixed = 20,
dml2_pmo_pstate_strategy_reserved_fw_drr_clamped = 20,
dml2_pmo_pstate_strategy_fw_drr = 21,
dml2_pmo_pstate_strategy_reserved_fw_drr_var = 22,
};
#define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw - dml2_pmo_pstate_strategy_na + 1)) - 1) << dml2_pmo_pstate_strategy_na)
#define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_vactive_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_vactive_drr)
#define PMO_DRR_FIXED_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_fw_drr - dml2_pmo_pstate_strategy_fw_vactive_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_vactive_drr)
#define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_clamped - dml2_pmo_pstate_strategy_fw_vactive_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_vactive_drr)
#define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_drr + 1)) - 1) << dml2_pmo_pstate_strategy_fw_drr)
#define PMO_FW_STRATEGY_MASK (((1 << (dml2_pmo_pstate_strategy_reserved_fw_drr_var - dml2_pmo_pstate_strategy_fw_svp + 1)) - 1) << dml2_pmo_pstate_strategy_fw_svp)
@ -671,7 +676,7 @@ struct dml2_pmo_init_data {
union {
struct {
/* populated once during initialization */
enum dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 1][PMO_DCN4_MAX_DISPLAYS];
enum dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2][PMO_DCN4_MAX_DISPLAYS];
enum dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2 * 2][PMO_DCN4_MAX_DISPLAYS];
enum dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 2][PMO_DCN4_MAX_DISPLAYS];
enum dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 24 * 2][PMO_DCN4_MAX_DISPLAYS];
@ -689,7 +694,7 @@ struct dml2_pmo_instance {
int disp_clk_vmin_threshold;
int mpc_combine_limit;
int odm_combine_limit;
int min_clock_table_size;
int mcg_clock_table_size;
union {
struct {