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arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

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[ Upstream commit a172c86931 ]

A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways
512 ways / 2 (Dcache is 2-way per set) = 256 sets.

So, correct the d-cache-sets info.

[1] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed8845 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Nishanth Menon 2021-11-12 22:26:40 -06:00 committed by Greg Kroah-Hartman
parent 75919207c1
commit a001a15ab3
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/ti/k3-j7200.dtsi
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@ -60,7 +60,7 @@ cpu0: cpu@0 {
i-cache-sets = <256>; i-cache-sets = <256>;
d-cache-size = <0x8000>; d-cache-size = <0x8000>;
d-cache-line-size = <64>; d-cache-line-size = <64>;
d-cache-sets = <128>; d-cache-sets = <256>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
}; };
@ -74,7 +74,7 @@ cpu1: cpu@1 {
i-cache-sets = <256>; i-cache-sets = <256>;
d-cache-size = <0x8000>; d-cache-size = <0x8000>;
d-cache-line-size = <64>; d-cache-line-size = <64>;
d-cache-sets = <128>; d-cache-sets = <256>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
}; };
}; };