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drm/amdgpu/gfx7: Fixup IP block soft reset
Use basically the same implementation as GFX8, except for the GFX7 specific MQD functions. Reset every block using the GRBM, then proceed to reset the GRBM and SEM blocks using the SRBM. Remove the redundant gfx_v7_0_update_cg() function. The soft reset now calls the clock and powergating functions of the IP block instead. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf
Alex Deucher
parent
ba004e4536
commit
9fb7ee45d6
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@ -3617,21 +3617,6 @@ static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
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}
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}
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static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
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bool enable)
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{
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gfx_v7_0_enable_gui_idle_interrupt(adev, false);
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/* order matters! */
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if (enable) {
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gfx_v7_0_enable_mgcg(adev, true);
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gfx_v7_0_enable_cgcg(adev, true);
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} else {
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gfx_v7_0_enable_cgcg(adev, false);
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gfx_v7_0_enable_mgcg(adev, false);
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}
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gfx_v7_0_enable_gui_idle_interrupt(adev, true);
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}
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static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
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bool enable)
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{
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@ -4550,80 +4535,99 @@ static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
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static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
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u32 tmp;
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struct amdgpu_device *adev = ip_block->adev;
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int i;
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int r;
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/* GRBM_STATUS */
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tmp = RREG32(mmGRBM_STATUS);
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if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
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GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
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GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
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GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
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GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
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GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
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grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
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GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
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grbm_soft_reset =
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1) |
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1) |
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CP, 1) |
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPF, 1) |
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPC, 1) |
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REG_SET_FIELD(0, GRBM_SOFT_RESET, SOFT_RESET_CPG, 1);
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if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
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grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
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}
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srbm_soft_reset =
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REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1) |
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REG_SET_FIELD(0, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
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/* GRBM_STATUS2 */
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tmp = RREG32(mmGRBM_STATUS2);
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if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
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grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
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/* SRBM_STATUS */
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tmp = RREG32(mmSRBM_STATUS);
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if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
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mutex_lock(&adev->srbm_mutex);
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cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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gfx_v7_0_deactivate_hqd(adev, 2);
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cik_srbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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if (grbm_soft_reset || srbm_soft_reset) {
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/* disable CG/PG */
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gfx_v7_0_fini_pg(adev);
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gfx_v7_0_update_cg(adev, false);
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/* stop the rlc */
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adev->gfx.rlc.funcs->stop(adev);
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/* Disable GFX parsing/prefetching */
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WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
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/* Disable MEC parsing/prefetching */
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WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
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if (grbm_soft_reset) {
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tmp = RREG32(mmGRBM_SOFT_RESET);
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tmp |= grbm_soft_reset;
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dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~grbm_soft_reset;
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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}
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if (srbm_soft_reset) {
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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}
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/* Wait a little for things to settle down */
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udelay(50);
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}
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ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
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ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
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ip_block->version->funcs->suspend(ip_block);
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if (grbm_soft_reset || srbm_soft_reset) {
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tmp = RREG32(mmGMCON_DEBUG);
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tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
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tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
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WREG32(mmGMCON_DEBUG, tmp);
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udelay(100);
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}
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if (grbm_soft_reset) {
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tmp = RREG32(mmGRBM_SOFT_RESET);
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tmp |= grbm_soft_reset;
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dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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udelay(100);
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tmp &= ~grbm_soft_reset;
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WREG32(mmGRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmGRBM_SOFT_RESET);
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udelay(100);
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}
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if (srbm_soft_reset) {
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tmp = RREG32(mmSRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(100);
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tmp &= ~srbm_soft_reset;
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WREG32(mmSRBM_SOFT_RESET, tmp);
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tmp = RREG32(mmSRBM_SOFT_RESET);
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udelay(100);
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}
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if (grbm_soft_reset || srbm_soft_reset) {
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tmp = RREG32(mmGMCON_DEBUG);
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tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
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tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
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WREG32(mmGMCON_DEBUG, tmp);
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}
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/* Wait a little for things to settle down */
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udelay(100);
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r = ip_block->version->funcs->resume(ip_block);
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r |= ip_block->version->funcs->late_init(ip_block);
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if (r)
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return r;
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ip_block->version->funcs->set_clockgating_state(ip_block, AMD_CG_STATE_GATE);
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ip_block->version->funcs->set_powergating_state(ip_block, AMD_PG_STATE_GATE);
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return 0;
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}
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