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clk: qcom: gcc-sdx75: Use common clock controller probe data
Move the always-on branch register offsets into a critical_cbcrs array and describe the DFS RCGs through qcom_cc_driver_data. Use qcom_cc_probe() to perform the common initialization instead of open-coding it in the driver's probe. Assisted-by: LLM Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-25-1479443ee016@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@ -2905,7 +2905,20 @@ static const struct regmap_config gcc_sdx75_regmap_config = {
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.fast_io = true,
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};
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static const u32 gcc_sdx75_critical_cbcrs[] = {
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0x3e004, /* GCC_AHB_PCIE_LINK_CLK */
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0x3e008, /* GCC_XO_PCIE_LINK_CLK */
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};
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static const struct qcom_cc_driver_data gcc_sdx75_driver_data = {
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.clk_cbcrs = gcc_sdx75_critical_cbcrs,
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.num_clk_cbcrs = ARRAY_SIZE(gcc_sdx75_critical_cbcrs),
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.dfs_rcgs = gcc_dfs_clocks,
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.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
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};
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static const struct qcom_cc_desc gcc_sdx75_desc = {
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.driver_data = &gcc_sdx75_driver_data,
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.config = &gcc_sdx75_regmap_config,
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.clks = gcc_sdx75_clocks,
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.num_clks = ARRAY_SIZE(gcc_sdx75_clocks),
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@ -2924,23 +2937,7 @@ MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table);
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static int gcc_sdx75_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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regmap = qcom_cc_map(pdev, &gcc_sdx75_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
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ARRAY_SIZE(gcc_dfs_clocks));
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if (ret)
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return ret;
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/* Keep some clocks always-on */
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qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */
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qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */
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return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap);
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return qcom_cc_probe(pdev, &gcc_sdx75_desc);
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}
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static struct platform_driver gcc_sdx75_driver = {
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