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drm/msm/adreno: Sync registers from mesa
Most of the churn is just reworking the usage attribute on the mesa
side.
Sync from mesa commit ff41a00fab89 ("freedreno/registers: Correct
register name")
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728202/
Message-ID: <20260526145137.160554-4-robin.clark@oss.qualcomm.com>
This commit is contained in:
Rob Clark
parent
e8c4d60f53
commit
9f860dbf0b
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@ -752,17 +752,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);
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/* Disable L2 bypass in the UCHE */
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gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));
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gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));
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gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base));
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gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base));
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gpu_write64(gpu, REG_A5XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);
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gpu_write64(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);
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/* Set the GMEM VA range (0 to gpu->gmem) */
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
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gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
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gpu_write64(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX,
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0x00100000 + adreno_gpu->info->gmem - 1);
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
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if (adreno_is_a505(adreno_gpu) || adreno_is_a506(adreno_gpu) ||
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adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
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@ -1217,9 +1213,7 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)
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static void a5xx_uche_err_irq(struct msm_gpu *gpu)
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{
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uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI);
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addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO);
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uint64_t addr = gpu_read64(gpu, REG_A5XX_UCHE_TRAP_LOG);
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dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n",
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addr);
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@ -1330,11 +1330,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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</reg32>
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<reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
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<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
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<!--
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not sure about full vs half const.. I can't get blob generate
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something with a mediump/lowp uniform.
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-->
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<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
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<bitfield name="CONSTMAXID" low="10" high="19" type="uint"/>
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<bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
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</reg32>
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<reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
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@ -1420,7 +1416,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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</reg32>
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<reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
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<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
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<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
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<bitfield name="CONSTMAXID" low="10" high="19" type="uint"/>
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<bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
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<bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
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</reg32>
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@ -1418,8 +1418,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
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<!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
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</reg32>
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<reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
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<reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
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<reg64 offset="0x0bc3" name="VSC_SIZE_ADDRESS" type="waddress"/>
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<reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
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<reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
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<array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
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@ -1498,12 +1497,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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</reg32>
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<reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
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<reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
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<reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
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<reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
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<reg64 offset="0x0d04" name="PC_INDEX_BUF" type="waddress"/>
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<reg32 offset="0x0d06" name="PC_START_INDEX"/>
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<reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
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<reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
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<reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
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<reg64 offset="0x0d08" name="PC_TESSFACTOR_ADDR" type="waddress"/>
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<reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
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<reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
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<reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
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@ -1555,20 +1552,14 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
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<reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
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<reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
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<reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
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<reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
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<reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
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<reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
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<reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
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<reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
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<reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
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<reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
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<reg64 offset="0x0e87" name="UCHE_WRITE_THRU_BASE" type="waddress"/>
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<reg64 offset="0x0e89" name="UCHE_TRAP_BASE" type="waddress"/>
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<reg64 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN" type="waddress"/>
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<reg64 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX" type="waddress"/>
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<reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
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<reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
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<reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
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<reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
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<reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
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<reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
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<reg64 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN" type="address"/>
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<reg64 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX" type="address"/>
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<reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
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<reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
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<reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
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@ -1583,8 +1574,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
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<reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
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<reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
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<reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
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<reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
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<reg64 offset="0x0eb1" name="UCHE_TRAP_LOG" type="waddress"/>
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<reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
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<reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
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@ -1923,8 +1913,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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invalidates the LRZ buffer? (Or just the covered positions?
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-->
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</reg32>
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<reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
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<reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
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<reg64 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
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<!--
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lzr pitch is depth pitch (in pixels) / 8 (aligned to 32)..
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-->
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@ -1933,8 +1922,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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is also divided by 8 (ie. covers 8x8 pixels)
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</doc>
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<reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
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<reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
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<reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
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<reg64 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
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<reg32 offset="0xe140" name="RB_CNTL">
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<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
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@ -2035,8 +2023,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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-->
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<reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
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<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
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<reg32 offset="0x5" name="BASE_LO"/>
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<reg32 offset="0x6" name="BASE_HI"/>
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<reg64 offset="0x5" name="BASE" type="waddress"/>
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</array>
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<reg32 offset="0xe1a0" name="RB_BLEND_RED">
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<bitfield name="UINT" low="0" high="7" type="hex"/>
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@ -2089,8 +2076,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
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<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
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</reg32>
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<reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
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<reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
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<reg64 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
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<reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
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<doc>stride of depth/stencil buffer</doc>
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</reg32>
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@ -2119,8 +2105,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
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<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
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</reg32>
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<reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
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<reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
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<reg64 offset="0xe1c2" name="RB_STENCIL_BASE" type="waddress"/>
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<reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
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<reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
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<reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
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@ -2163,8 +2148,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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also for gmem->mem preserving tiling
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-->
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</reg32>
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<reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
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<reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
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<reg64 offset="0xe214" name="RB_BLIT_DST" type="waddress"/>
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<reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
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<!-- array-pitch is size of layer -->
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<reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
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@ -2235,25 +2219,22 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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</doc>
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<reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
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<reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
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<reg64 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
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<reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
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</reg32>
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<array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
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<reg32 offset="0" name="ADDR_LO"/>
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<reg64 offset="0" name="ADDR" type="waddress"/>
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<reg32 offset="1" name="ADDR_HI"/>
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<reg32 offset="2" name="PITCH" shr="6" type="uint"/>
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<!-- array-pitch is size of layer -->
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<reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/>
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</array>
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<reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
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<reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
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<reg64 offset="0xe263" name="RB_BLIT_FLAG_DST" type="waddress"/>
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<reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
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<!-- array-pitch is size of layer -->
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<reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
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<reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
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<reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
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<reg64 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR" type="waddress"/>
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<reg32 offset="0xe280" name="VPC_CNTL_0">
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<doc>
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@ -2357,13 +2338,11 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<bitfield name="B_EN" pos="23" type="boolean"/>
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</reg32>
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<array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
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<reg32 offset="0" name="BUFFER_BASE_LO"/>
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<reg32 offset="1" name="BUFFER_BASE_HI"/>
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<reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
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<reg32 offset="2" name="BUFFER_SIZE"/>
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<reg32 offset="3" name="NCOMP"/> <!-- component count -->
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<reg32 offset="4" name="BUFFER_OFFSET"/>
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<reg32 offset="5" name="FLUSH_BASE_LO"/>
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<reg32 offset="6" name="FLUSH_BASE_HI"/>
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<reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
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</array>
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<reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
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@ -2423,8 +2402,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
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<reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
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<array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
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<reg32 offset="0x0" name="BASE_LO"/>
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<reg32 offset="0x1" name="BASE_HI"/>
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<reg64 offset="0x0" name="BASE" type="address"/>
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<reg32 offset="0x2" name="SIZE" type="uint"/>
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<reg32 offset="0x3" name="STRIDE" type="uint"/>
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</array>
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@ -2475,7 +2453,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<bitfield name="VARYING" pos="16" type="boolean"/>
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<bitfield name="PIXLODENABLE" pos="20" type="boolean"/>
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<!-- seems to be nesting level for flow control:.. -->
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<bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/>
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<bitfield name="BRANCHSTACK" low="24" high="31" type="uint"/>
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</bitset>
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<!-- assuming things appear in same relative order as a4xx: -->
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<!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
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@ -2516,8 +2494,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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</reg32>
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</array>
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<reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
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<reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
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<reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
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<reg64 offset="0xe5ac" name="SP_VS_OBJ_START" type="address"/>
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<bitset name="a5xx_sp_xs_pvt_mem_param" inline="yes">
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<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
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@ -2538,8 +2515,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
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<reg32 offset="0xe5b1" name="SP_VS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
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<reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
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<reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
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<reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
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<reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
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<reg64 offset="0xe5c3" name="SP_FS_OBJ_START" type="address"/>
|
||||
<reg32 offset="0xe5c5" name="SP_FS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
|
||||
<reg64 offset="0xe5c6" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
|
||||
<reg32 offset="0xe5c8" name="SP_FS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
|
||||
|
|
@ -2577,8 +2553,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
|
|||
<reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
|
||||
<reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
|
||||
<reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
|
||||
<reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
|
||||
<reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
|
||||
<reg64 offset="0xe5f3" name="SP_CS_OBJ_START" type="address"/>
|
||||
<reg32 offset="0xe5f5" name="SP_CS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
|
||||
<reg64 offset="0xe5f6" name="SP_CS_PVT_MEM_ADDR" type="waddress" align="32"/>
|
||||
<reg32 offset="0xe5f8" name="SP_CS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
|
||||
|
|
@ -2587,22 +2562,19 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
|
|||
|
||||
<reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
|
||||
<reg32 offset="0xe602" name="UNKNOWN_E602"/>
|
||||
<reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
|
||||
<reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
|
||||
<reg64 offset="0xe603" name="SP_HS_OBJ_START" type="address"/>
|
||||
<reg32 offset="0xe605" name="SP_HS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
|
||||
<reg64 offset="0xe606" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
|
||||
<reg32 offset="0xe608" name="SP_HS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
|
||||
<reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
|
||||
<reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
|
||||
<reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
|
||||
<reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
|
||||
<reg64 offset="0xe62c" name="SP_DS_OBJ_START" type="address"/>
|
||||
<reg32 offset="0xe62e" name="SP_DS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
|
||||
<reg64 offset="0xe62f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
|
||||
<reg32 offset="0xe631" name="SP_DS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
|
||||
<reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
|
||||
<reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
|
||||
<reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
|
||||
<reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
|
||||
<reg64 offset="0xe65c" name="SP_GS_OBJ_START" type="address"/>
|
||||
<reg32 offset="0xe65e" name="SP_GS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
|
||||
<reg64 offset="0xe65f" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
|
||||
<reg32 offset="0xe661" name="SP_GS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
|
||||
|
|
@ -2615,8 +2587,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
|
|||
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
|
||||
</reg32>
|
||||
<!-- either blob is doing it wrong, or this is not per-stage anymore: -->
|
||||
<reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
|
||||
<reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
|
||||
<reg64 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
|
||||
|
||||
<!--
|
||||
so these have the same info that is normally in the CP_LOAD_STATE
|
||||
|
|
@ -2628,35 +2599,23 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
|
|||
<reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
|
||||
<reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
|
||||
|
||||
<reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
|
||||
<reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
|
||||
<reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
|
||||
<reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
|
||||
<reg64 offset="0xe722" name="TPL1_VS_TEX_SAMP" type="address"/>
|
||||
<reg64 offset="0xe724" name="TPL1_HS_TEX_SAMP" type="address"/>
|
||||
<reg64 offset="0xe726" name="TPL1_DS_TEX_SAMP" type="address"/>
|
||||
<reg64 offset="0xe728" name="TPL1_GS_TEX_SAMP" type="address"/>
|
||||
|
||||
<reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
|
||||
<reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
|
||||
<reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
|
||||
<reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
|
||||
<reg64 offset="0xe72a" name="TPL1_VS_TEX_CONST" type="address"/>
|
||||
<reg64 offset="0xe72c" name="TPL1_HS_TEX_CONST" type="address"/>
|
||||
<reg64 offset="0xe72e" name="TPL1_DS_TEX_CONST" type="address"/>
|
||||
<reg64 offset="0xe730" name="TPL1_GS_TEX_CONST" type="address"/>
|
||||
|
||||
<reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
|
||||
<reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
|
||||
|
||||
<reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
|
||||
<reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
|
||||
<reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
|
||||
<reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
|
||||
<reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
|
||||
<reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
|
||||
<reg64 offset="0xe75a" name="TPL1_FS_TEX_SAMP" type="address"/>
|
||||
<reg64 offset="0xe75c" name="TPL1_CS_TEX_SAMP" type="address"/>
|
||||
<reg64 offset="0xe75e" name="TPL1_FS_TEX_CONST" type="address"/>
|
||||
<reg64 offset="0xe760" name="TPL1_CS_TEX_CONST" type="address"/>
|
||||
|
||||
<reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
|
||||
|
||||
|
|
@ -2809,25 +2768,21 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
|
|||
</bitset>
|
||||
|
||||
<reg32 offset="0x2107" name="RB_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
|
||||
<reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
|
||||
<reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
|
||||
<reg64 offset="0x2108" name="RB_2D_SRC" type="address"/>
|
||||
<reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
|
||||
<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
|
||||
<bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
|
||||
</reg32>
|
||||
|
||||
<reg32 offset="0x2110" name="RB_2D_DST_INFO" type="a5xx_2d_surf_info"/>
|
||||
<reg32 offset="0x2111" name="RB_2D_DST_LO"/>
|
||||
<reg32 offset="0x2112" name="RB_2D_DST_HI"/>
|
||||
<reg64 offset="0x2111" name="RB_2D_DST" type="address"/>
|
||||
<reg32 offset="0x2113" name="RB_2D_DST_SIZE">
|
||||
<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
|
||||
<bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
|
||||
</reg32>
|
||||
<reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
|
||||
<reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
|
||||
<reg64 offset="0x2140" name="RB_2D_SRC_FLAGS" type="address"/>
|
||||
<reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
|
||||
<reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
|
||||
<reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
|
||||
<reg64 offset="0x2143" name="RB_2D_DST_FLAGS" type="address"/>
|
||||
<reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
|
||||
<reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
|
||||
<!-- looks same as 0x2107: -->
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -45,19 +45,21 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<reg32 offset="3" name="3"/>
|
||||
</domain>
|
||||
|
||||
<domain name="A6XX_TEX_CONST" width="32" varset="chip">
|
||||
<domain name="A6XX_TEX_MEMOBJ" width="32" varset="desctype">
|
||||
<doc>Texture constant dwords</doc>
|
||||
<reg32 offset="0" name="0">
|
||||
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
|
||||
<bitfield name="SRGB" pos="2" type="boolean"/>
|
||||
<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
|
||||
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
|
||||
<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="MIPLVLS" low="16" high="19" type="uint" variants="DESC_SINGLE_PLANE DESC_BUFFER DESC_WEIGHT"/>
|
||||
|
||||
<!-- overlaps with MIPLVLS -->
|
||||
<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
|
||||
<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
|
||||
<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean" variants="DESC_MULTI_PLANE"/>
|
||||
<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean" variants="DESC_MULTI_PLANE"/>
|
||||
|
||||
<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
|
||||
<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
|
||||
<!--
|
||||
|
|
@ -68,9 +70,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
|
||||
</reg32>
|
||||
<reg32 offset="1" name="1">
|
||||
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
|
||||
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
|
||||
<bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>
|
||||
<bitfield name="WIDTH" low="0" high="14" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="HEIGHT" low="15" high="29" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="NUM_ELEMENTS" low="0" high="29" type="uint" variants="DESC_BUFFER"/>
|
||||
<bitfield name="MUTABLEEN" pos="31" type="boolean"/> <!-- a7xx+ -->
|
||||
</reg32>
|
||||
<reg32 offset="2" name="2">
|
||||
<!--
|
||||
|
|
@ -78,13 +81,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.
|
||||
-->
|
||||
<doc> probably for D3D structured UAVs, normally set to 1 </doc>
|
||||
<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
|
||||
<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
|
||||
<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint" variants="DESC_BUFFER"/>
|
||||
<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint" variants="DESC_BUFFER"/>
|
||||
|
||||
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
|
||||
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
|
||||
<bitfield name="PITCHALIGN" low="0" high="3" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<doc>Pitch in bytes (so actually stride)</doc>
|
||||
<bitfield name="PITCH" low="7" high="28" type="uint"/>
|
||||
<bitfield name="PITCH" low="7" high="28" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
|
||||
</reg32>
|
||||
<reg32 offset="3" name="3">
|
||||
|
|
@ -94,15 +97,15 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
layer size at the point that it stops being reduced moving to
|
||||
higher (smaller) mipmap levels
|
||||
-->
|
||||
<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
|
||||
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
|
||||
<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12" variants="DESC_SINGLE_PLANE"/>
|
||||
<!--
|
||||
by default levels with w < 16 are linear
|
||||
TILE_ALL makes all levels have tiling
|
||||
seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
|
||||
-->
|
||||
<bitfield name="TILE_ALL" pos="27" type="boolean"/>
|
||||
<bitfield name="FLAG" pos="28" type="boolean"/>
|
||||
<bitfield name="TILE_ALL" pos="27" type="boolean" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="FLAG" pos="28" type="boolean" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
|
||||
the address of the non-flag base buffer is determined automatically,
|
||||
|
|
@ -113,30 +116,42 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
</reg32>
|
||||
<reg32 offset="5" name="5">
|
||||
<bitfield name="BASE_HI" low="0" high="16"/>
|
||||
<bitfield name="DEPTH" low="17" high="29" type="uint"/>
|
||||
<bitfield name="DEPTH" low="17" high="29" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<reg32 offset="6" name="6">
|
||||
<!-- overlaps with PLANE_PITCH -->
|
||||
<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
|
||||
<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE"/>
|
||||
<!-- pitch for plane 2 / plane 3 -->
|
||||
<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
|
||||
<bitfield name="PLANE_PITCH" low="8" high="31" type="uint" variants="DESC_MULTI_PLANE"/>
|
||||
|
||||
<!-- QCOM_image_filtering sample weights descriptor fields, overlapping the others. -->
|
||||
<bitfield name="LOG2_PHASES" low="0" high="2" type="uint" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="DILATION" low="8" high="11" type="uint" variants="DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<!-- 7/8 is plane 2 address for planar formats -->
|
||||
<reg32 offset="7" name="7">
|
||||
<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
|
||||
<bitfield name="FLAG_LO" low="5" high="31" shr="5" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="BASE_U_LO" low="5" high="31" shr="5" variants="DESC_MULTI_PLANE"/>
|
||||
</reg32>
|
||||
<reg32 offset="8" name="8">
|
||||
<bitfield name="FLAG_HI" low="0" high="16"/>
|
||||
<bitfield name="FLAG_HI" low="0" high="16" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="BASE_U_HI" low="0" high="16" variants="DESC_MULTI_PLANE"/>
|
||||
<bitfield name="FILTER_SIZE_X" low="17" high="23" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="FILTER_SIZE_Y" low="24" high="30" variants="DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<!-- 9/10 is plane 3 address for planar formats -->
|
||||
<reg32 offset="9" name="9">
|
||||
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="BASE_V_LO" low="5" high="31" shr="5" variants="DESC_MULTI_PLANE"/>
|
||||
</reg32>
|
||||
<reg32 offset="10" name="10">
|
||||
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<!-- log2 size of the first level, required for mipmapping -->
|
||||
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="BASE_V_HI" low="0" high="16" variants="DESC_MULTI_PLANE"/>
|
||||
<bitfield name="FILTER_OFFSET_X" low="17" high="22" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="FILTER_OFFSET_Y" low="23" high="28" variants="DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<reg32 offset="11" name="11"/>
|
||||
<reg32 offset="12" name="12"/>
|
||||
|
|
|
|||
|
|
@ -328,6 +328,9 @@ to upconvert to 32b float internally?
|
|||
<value value="0x2" name="R2D_SNORM8"/>
|
||||
<value value="0x1" name="R2D_UNORM8_SRGB"/>
|
||||
<value value="0x0" name="R2D_UNORM8"/>
|
||||
|
||||
<!-- Not a hw enum, used internally in driver -->
|
||||
<value value="0xff" name="R2D_NONE"/>
|
||||
</enum>
|
||||
|
||||
<enum name="a6xx_tex_type">
|
||||
|
|
|
|||
|
|
@ -39,76 +39,92 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<reg32 offset="3" name="3"/>
|
||||
</domain>
|
||||
|
||||
<domain name="A8XX_TEX_MEMOBJ" width="32" varset="chip">
|
||||
<domain name="A8XX_TEX_MEMOBJ" width="32" varset="desctype">
|
||||
<doc>Texture memobj dwords</doc>
|
||||
<reg32 offset="0" name="0">
|
||||
<bitfield name="BASE_LO" low="6" high="31" shr="6"/>
|
||||
<bitfield name="BASE_LO" low="6" high="31" shr="6" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<doc>for type TEX_BUFFER</doc>
|
||||
<bitfield name="INSTANCE_DESC_BASE_LO" low="0" high="31" variants="DESC_BUFFER"/>
|
||||
</reg32>
|
||||
<reg32 offset="1" name="1">
|
||||
<bitfield name="BASE_HI" low="0" high="16"/>
|
||||
<bitfield name="BASE_HI" low="0" high="16" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="INSTANCE_DESC_BASE_HI" low="0" high="16" variants="DESC_BUFFER"/>
|
||||
<bitfield name="TYPE" low="17" high="19" type="a6xx_tex_type"/>
|
||||
<bitfield name="DEPTH" low="20" high="31" type="uint"/>
|
||||
<bitfield name="DEPTH" low="20" high="31" type="uint" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
<doc> for type TEX_BUFFER, probably for D3D structured UAVs, normally set to 1 </doc>
|
||||
<bitfield name="STRUCTSIZETEXELS" low="20" high="31" type="uint" variants="DESC_BUFFER"/>
|
||||
</reg32>
|
||||
<reg32 offset="2" name="2">
|
||||
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
|
||||
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
|
||||
<bitfield name="SAMPLES" low="30" high="31" type="a3xx_msaa_samples"/>
|
||||
<bitfield name="WIDTH" low="0" high="14" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="HEIGHT" low="15" high="29" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="SAMPLES" low="30" high="31" type="a3xx_msaa_samples" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="NUM_ELEMENTS" low="0" high="31" type="uint" variants="DESC_BUFFER"/>
|
||||
</reg32>
|
||||
<reg32 offset="3" name="3">
|
||||
<bitfield name="FMT" low="0" high="7" type="a6xx_format"/>
|
||||
<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
|
||||
<bitfield name="SWIZ_X" low="10" high="12" type="a8xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_Y" low="13" high="15" type="a8xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_Z" low="16" high="18" type="a8xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_W" low="19" high="21" type="a8xx_tex_swiz"/>
|
||||
<bitfield name="SWIZ_X" low="10" high="12" type="a8xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_Y" low="13" high="15" type="a8xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_Z" low="16" high="18" type="a8xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
<bitfield name="SWIZ_W" low="19" high="21" type="a8xx_tex_swiz" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_BUFFER"/>
|
||||
</reg32>
|
||||
<reg32 offset="4" name="4">
|
||||
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
|
||||
<bitfield name="FLAG" pos="2" type="boolean"/>
|
||||
<bitfield name="PRT_EN" pos="3" type="boolean"/>
|
||||
<bitfield name="TILE_ALL" pos="4" type="boolean"/>
|
||||
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="FLAG" pos="2" type="boolean" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="PRT_EN" pos="3" type="boolean" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
<bitfield name="TILE_ALL" pos="4" type="boolean" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="SRGB" pos="5" type="boolean"/>
|
||||
<bitfield name="FLAG_LO" low="6" high="31" shr="6"/>
|
||||
<bitfield name="FLAG_LO" low="6" high="31" shr="6" variants="DESC_SINGLE_PLANE"/>
|
||||
<!-- For multiplanar: -->
|
||||
<bitfield name="BASE_U_LO" low="6" high="31" shr="6"/>
|
||||
<bitfield name="BASE_U_LO" low="6" high="31" shr="6" variants="DESC_MULTI_PLANE"/>
|
||||
</reg32>
|
||||
<reg32 offset="5" name="5">
|
||||
<bitfield name="FLAG_HI" low="0" high="16"/>
|
||||
<bitfield name="FLAG_HI" low="0" high="16" variants="DESC_SINGLE_PLANE"/>
|
||||
<!-- For multiplanar: -->
|
||||
<bitfield name="BASE_U_HI" low="0" high="16"/>
|
||||
<bitfield name="FLAG_BUFFER_PITCH" low="17" high="24" shr="6" type="uint"/>
|
||||
<bitfield name="ALL_SAMPLES_CENTER" pos="29" type="boolean"/>
|
||||
<bitfield name="MUTABLEEN" pos="31" type="boolean"/>
|
||||
<bitfield name="BASE_U_HI" low="0" high="16" variants="DESC_MULTI_PLANE"/>
|
||||
<bitfield name="FLAG_BUFFER_PITCH" low="17" high="24" shr="6" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE"/>
|
||||
<bitfield name="ALL_SAMPLES_CENTER" pos="29" type="boolean" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="MUTABLEEN" pos="31" type="boolean" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
|
||||
<!-- QCOM_image_filtering sample weights descriptor fields, overlapping the others. -->
|
||||
<bitfield name="FILTER_SIZE_X" low="0" high="6" type="uint" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="FILTER_SIZE_Y" low="7" high="13" type="uint" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="FILTER_OFFSET_X" low="19" high="24" type="uint" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="FILTER_OFFSET_Y" low="25" high="30" type="uint" variants="DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<reg32 offset="6" name="6">
|
||||
<bitfield name="TEX_LINE_OFFSET" low="0" high="23" type="uint"/> <!-- PITCH -->
|
||||
<bitfield name="MIN_LINE_OFFSET" low="24" high="27" type="uint"/> <!-- PITCHALIGN -->
|
||||
<bitfield name="MIPLVLS" low="28" high="31" type="uint"/>
|
||||
<bitfield name="TEX_LINE_OFFSET" low="0" high="23" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/> <!-- PITCH -->
|
||||
<bitfield name="MIN_LINE_OFFSET" low="24" high="27" type="uint" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/> <!-- PITCHALIGN -->
|
||||
<bitfield name="MIPLVLS" low="28" high="31" type="uint" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<reg32 offset="7" name="7">
|
||||
<bitfield name="ARRAY_SLICE_OFFSET" low="0" high="22" shr="12" type="uint"/> <!-- ARRAY_PITCH -->
|
||||
<bitfield name="ASO_UNIT" pos="23"/> <!-- 4KB or 32B ? -->
|
||||
<bitfield name="MIN_ARRAY_SLIZE_OFFSET" low="24" high="27" shr="12"/> <!-- MIN_LAYERSZ -->
|
||||
<bitfield name="GMEM_TILING_FALLBACK_EN" pos="28" type="boolean"/>
|
||||
<bitfield name="CORNER_BASED_EN" pos="30" type="boolean"/>
|
||||
<bitfield name="GMEM_FULL_SURF" pos="31" type="boolean"/>
|
||||
<bitfield name="ARRAY_SLICE_OFFSET" low="0" high="22" shr="12" type="uint" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/> <!-- ARRAY_PITCH -->
|
||||
<bitfield name="ASO_UNIT" pos="23" variants="DESC_SINGLE_PLANE DESC_WEIGHT"/> <!-- 4KB or 32B ? -->
|
||||
<bitfield name="MIN_ARRAY_SLIZE_OFFSET" low="24" high="27" shr="12" variants="DESC_SINGLE_PLANE"/> <!-- MIN_LAYERSZ -->
|
||||
<bitfield name="GMEM_TILING_FALLBACK_EN" pos="28" type="boolean" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="CORNER_BASED_EN" pos="30" type="boolean" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE"/>
|
||||
<bitfield name="GMEM_FULL_SURF" pos="31" type="boolean" variants="DESC_SINGLE_PLANE DESC_MULTI_PLANE DESC_WEIGHT"/>
|
||||
<!-- For multiplanar. This overlaps other single-planar fields: -->
|
||||
<bitfield name="UV_OFFSET_H" low="24" high="25" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_X -->
|
||||
<bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2"/> <!-- CHROMA_MIDPOINT_Y -->
|
||||
<bitfield name="UV_OFFSET_H" low="24" high="25" type="ufixed" radix="2" variants="DESC_MULTI_PLANE"/> <!-- CHROMA_MIDPOINT_X -->
|
||||
<bitfield name="UV_OFFSET_V" low="26" high="27" type="ufixed" radix="2" variants="DESC_MULTI_PLANE"/> <!-- CHROMA_MIDPOINT_Y -->
|
||||
|
||||
<!-- QCOM_image_filtering sample weights descriptor fields, overlapping the others. -->
|
||||
<bitfield name="DILATION" low="24" high="27" type="uint" variants="DESC_WEIGHT"/>
|
||||
<bitfield name="LOG2_PHASES" low="28" high="30" type="uint" variants="DESC_WEIGHT"/>
|
||||
</reg32>
|
||||
<reg32 offset="8" name="8">
|
||||
<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
|
||||
<bitfield name="FLAG_ARRAY_PITCH" low="0" high="14" shr="12" type="uint" variants="DESC_SINGLE_PLANE"/> <!-- FLAG_BUFFER_ARRAY_PITCH -->
|
||||
<!-- log2 size of the first level, required for mipmapping -->
|
||||
<bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGW" low="24" high="27" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<bitfield name="FLAG_BUFFER_LOGH" low="28" high="31" type="uint" variants="DESC_SINGLE_PLANE"/>
|
||||
<!-- For multiplanar. This overlaps other single-planar fields: -->
|
||||
<bitfield name="BASE_V_LO" low="6" high="31" shr="6"/>
|
||||
<bitfield name="BASE_V_LO" low="6" high="31" shr="6" variants="DESC_MULTI_PLANE"/>
|
||||
</reg32>
|
||||
<reg32 offset="9" name="9">
|
||||
<bitfield name="MIN_LOD_CLAMP" low="19" high="30" type="ufixed" radix="8"/>
|
||||
<bitfield name="MIN_LOD_CLAMP" low="19" high="30" type="ufixed" radix="8" variants="DESC_SINGLE_PLANE"/>
|
||||
<!-- For multiplanar, this overlaps other fields: -->
|
||||
<bitfield name="BASE_V_HI" low="0" high="16"/>
|
||||
<bitfield name="UV_PITCH" low="17" high="26"/> <!-- PLANE_PITCH -->
|
||||
<bitfield name="BASE_V_HI" low="0" high="16" variants="DESC_MULTI_PLANE"/>
|
||||
<bitfield name="UV_PITCH" shr="6" low="17" high="26" variants="DESC_MULTI_PLANE"/> <!-- PLANE_PITCH -->
|
||||
</reg32>
|
||||
<reg32 offset="10" name="10"/>
|
||||
<reg32 offset="11" name="11"/>
|
||||
|
|
|
|||
1929
drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml
Normal file
1929
drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -14,6 +14,27 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<value name="A8XX" value="8"/>
|
||||
</enum>
|
||||
|
||||
<enum name="desctype" bare="yes">
|
||||
<value name="DESC_NONE" value="0"/>
|
||||
<doc>
|
||||
TEX_MEMOBJ descriptor types. These are used
|
||||
to mark fields that only apply to certain
|
||||
descriptor types, and potentially overlap
|
||||
with fields in other types.
|
||||
</doc>
|
||||
<value name="DESC_SINGLE_PLANE" value="1"/>
|
||||
<value name="DESC_MULTI_PLANE" value="2"/>
|
||||
<value name="DESC_BUFFER" value="3"/>
|
||||
<value name="DESC_WEIGHT" value="4"/>
|
||||
<doc>
|
||||
Additional descriptor types not part of
|
||||
TEX_MEMOBJ. These are described by their
|
||||
own toplevel domain.
|
||||
</doc>
|
||||
<value name="DESC_SAMPLER" value="10"/> <!-- AxXX_UBO -->
|
||||
<value name="DESC_UBO" value="11"/> <!-- A6XX_UBO, same on gen8 -->
|
||||
</enum>
|
||||
|
||||
<enum name="adreno_pa_su_sc_draw">
|
||||
<value name="PC_DRAW_POINTS" value="0"/>
|
||||
<value name="PC_DRAW_LINES" value="1"/>
|
||||
|
|
@ -409,4 +430,25 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<value value="7" name="PIPE_DDE_BV"/>
|
||||
</enum>
|
||||
|
||||
<!--
|
||||
A fake domain for giving lua scripts access to the shader_stats struct
|
||||
-->
|
||||
<domain name="ir3_shader_stats" width="32">
|
||||
<!-- indx 0 is bindful, indx N+1 is .baseN -->
|
||||
<array offset="0" name="descriptor_stats" stride="8" length="9">
|
||||
<reg64 offset="0" name="img"/>
|
||||
<reg64 offset="2" name="tex"/>
|
||||
<reg64 offset="4" name="samp"/>
|
||||
<reg64 offset="6" name="ubo"/>
|
||||
</array>
|
||||
<reg32 offset="72" name="has_img"/>
|
||||
<reg32 offset="73" name="has_tex"/>
|
||||
<reg32 offset="74" name="has_samp"/>
|
||||
<reg32 offset="74" name="has_ubo"/>
|
||||
<!--
|
||||
other following fields can be added as needed, but we
|
||||
might need to take care of padding/alignment.
|
||||
-->
|
||||
</domain>
|
||||
|
||||
</database>
|
||||
|
|
|
|||
|
|
@ -152,6 +152,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<!-- TODO: deal with name conflicts with other gens -->
|
||||
<value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/>
|
||||
<value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/>
|
||||
<value name="SUBPASS_FENCE" value="0x35" variants="A7XX-"/>
|
||||
<value name="SUBPASS_SLICE_FENCE" value="0x36" variants="A8XX-"/>
|
||||
<value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/>
|
||||
<value name="CCH_FAST_CLEAR_CLEAN" value="0x1b" variants="A8XX-"/>
|
||||
</enum>
|
||||
|
|
@ -1095,7 +1097,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<bitfield name="DIRTY" pos="16" type="boolean"/>
|
||||
<bitfield name="DISABLE" pos="17" type="boolean"/>
|
||||
<bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
|
||||
<bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
|
||||
<bitfield name="LOAD_IMMED" pos="19" type="boolean" variants="A5XX"/>
|
||||
<bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
|
||||
<bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
|
||||
<bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
|
||||
|
|
@ -1275,8 +1277,15 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<domain name="CP_REG_TO_MEM" width="32" prefix="chip">
|
||||
<reg32 offset="0" name="0">
|
||||
<bitfield name="REG" low="0" high="17" type="hex"/>
|
||||
<!-- number of registers/dwords copied is max(CNT, 1). -->
|
||||
<!--
|
||||
Number of registers/dwords copied is max(CNT, 1).
|
||||
With 64B it gets rounded to the next 64B boundary.
|
||||
-->
|
||||
<bitfield name="CNT" low="18" high="29" type="uint"/>
|
||||
<!--
|
||||
Treat things as 64B, allowing for a 64B atomic read of
|
||||
registers.
|
||||
-->
|
||||
<bitfield name="64B" pos="30" type="boolean"/>
|
||||
<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
|
||||
</reg32>
|
||||
|
|
@ -1469,6 +1478,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<value value="1" name="POLL_MEMORY"/>
|
||||
<value value="2" name="POLL_SCRATCH"/>
|
||||
<value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
|
||||
<value value="4" name="POLL_SYSTEM_VARIABLE" varset="chip" variants="A8XX-"/>
|
||||
</enum>
|
||||
|
||||
<domain name="CP_COND_WRITE5" width="32">
|
||||
|
|
@ -1476,7 +1486,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
|
||||
<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
|
||||
<!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
|
||||
<bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
|
||||
<bitfield name="POLL" low="4" high="6" type="poll_memory_type"/>
|
||||
<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
|
||||
</reg32>
|
||||
<reg64 offset="1" name="POLL_ADDR" type="address"/>
|
||||
|
|
@ -2055,28 +2065,20 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
|
||||
<domain name="CP_COND_EXEC" width="32">
|
||||
<doc>
|
||||
Executes the following DWORDs of commands if the dword at ADDR0
|
||||
is not equal to 0 and the dword at ADDR1 is less than REF
|
||||
(signed comparison).
|
||||
Executes the following DWORDs of commands if the dword
|
||||
at BOOL_ADDR is not equal to 0 and the the timestamp
|
||||
value ACTIVE_TIMESTAMP is ahead of the value fetched
|
||||
from TIMESTAMP_ADDR.
|
||||
|
||||
The timestamp comparision is an unsigned compare with
|
||||
wraparound, ie:
|
||||
|
||||
(ACTIVE_TIMESTAMP - *TIMESTAMP_ADDR) < 0x80000000
|
||||
</doc>
|
||||
<reg32 offset="0" name="0">
|
||||
<bitfield name="ADDR0_LO" low="0" high="31"/>
|
||||
</reg32>
|
||||
<reg32 offset="1" name="1">
|
||||
<bitfield name="ADDR0_HI" low="0" high="31"/>
|
||||
</reg32>
|
||||
<reg32 offset="2" name="2">
|
||||
<bitfield name="ADDR1_LO" low="0" high="31"/>
|
||||
</reg32>
|
||||
<reg32 offset="3" name="3">
|
||||
<bitfield name="ADDR1_HI" low="0" high="31"/>
|
||||
</reg32>
|
||||
<reg32 offset="4" name="4">
|
||||
<bitfield name="REF" low="0" high="31"/>
|
||||
</reg32>
|
||||
<reg32 offset="5" name="5">
|
||||
<bitfield name="DWORDS" low="0" high="31" type="uint"/>
|
||||
</reg32>
|
||||
<reg64 offset="0" name="BOOL_ADDR" type="address"/>
|
||||
<reg64 offset="2" name="TIMESTAMP_ADDR" type="address"/>
|
||||
<reg32 offset="4" name="ACTIVE_TIMESTAMP"/>
|
||||
<reg32 offset="5" name="DWORDS"/>
|
||||
</domain>
|
||||
|
||||
<domain name="CP_SET_AMBLE" width="32">
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user