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drm/amd/pm: Use emit_clk_levels in SMUv13.0.0

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Move to emit_clk_levels from print_clk_levels

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar 2025-11-26 12:55:37 +05:30 committed by Alex Deucher
parent b824bf6389
commit 9f63bcbace
1 changed files with 10 additions and 11 deletions
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21
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
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@ -1184,27 +1184,24 @@ static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
return ret;
}
static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
char *buf)
static int smu_v13_0_0_emit_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf,
int *offset)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
OverDriveTableExternal_t *od_table =
(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
int i, curr_freq, size = *offset, start_offset = *offset;
struct smu_13_0_dpm_table *single_dpm_table;
struct smu_13_0_pcie_table *pcie_table;
uint32_t gen_speed, lane_width;
int i, curr_freq, size = 0, start_offset = 0;
int32_t min_value, max_value;
int ret = 0;
smu_cmn_get_sysfs_buf(&buf, &size);
start_offset = size;
if (amdgpu_ras_intr_triggered()) {
size += sysfs_emit_at(buf, size, "unavailable\n");
return size - start_offset;
sysfs_emit_at(buf, size, "unavailable\n");
return -EBUSY;
}
switch (clk_type) {
@ -1535,7 +1532,9 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
break;
}
return size - start_offset;
*offset += size - start_offset;
return 0;
}
@ -3227,7 +3226,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
.read_sensor = smu_v13_0_0_read_sensor,
.feature_is_enabled = smu_cmn_feature_is_enabled,
.print_clk_levels = smu_v13_0_0_print_clk_levels,
.emit_clk_levels = smu_v13_0_0_emit_clk_levels,
.force_clk_levels = smu_v13_0_0_force_clk_levels,
.update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
.get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,