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clk: renesas: Updates for v5.19
- Add support for the new RZ/G2UL SoC, - Add RPC (QSPI/HyperFlash) clocks on R-Car E3 and D3, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYmKBOgAKCRCKwlD9ZEnx cJpcAPoDAsDq73zeTpcSVFITtdn893OgSJ3g9Z0i4fRJ6W75lwEAq9UJj/7cPzU4 Rqx6wsWBkq90aF0tzI6pw76j3zetBAY= =dAc8 -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new RZ/G2UL SoC - Add RPC (QSPI/HyperFlash) clocks on R-Car E3 and D3 - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a07g043: Add SDHI clock and reset entries clk: renesas: r9a07g043: Add GbEthernet clock/reset clk: renesas: r9a07g043: Add ethernet clock sources clk: renesas: r9a07g043: Add GPIO clock and reset entries clk: renesas: Add support for RZ/G2UL SoC clk: renesas: Move RPC core clocks clk: renesas: rzg2l: Simplify multiplication/shift logic dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions clk: renesas: r8a77995: Add RPC clocks clk: renesas: r8a77990: Add RPC clocks dt-bindings: clock: renesas: Document RZ/G2UL SoC clk: renesas: rzg2l: Remove unused notifiers
This commit is contained in:
Stephen Boyd
commit
9f4f53efa9
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@ -10,7 +10,7 @@ maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
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On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
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Standby Mode share the same register block.
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They provide the following functionalities:
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@ -23,8 +23,9 @@ description: |
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properties:
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compatible:
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enum:
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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reg:
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maxItems: 1
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@ -33,6 +33,7 @@ config CLK_RENESAS
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select CLK_R8A779A0 if ARCH_R8A779A0
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select CLK_R8A779F0 if ARCH_R8A779F0
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select CLK_R9A06G032 if ARCH_R9A06G032
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select CLK_R9A07G043 if ARCH_R9A07G043
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_SH73A0 if ARCH_SH73A0
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@ -160,6 +161,10 @@ config CLK_R8A779F0
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config CLK_R9A06G032
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bool "RZ/N1D clock support" if COMPILE_TEST
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config CLK_R9A07G043
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bool "RZ/G2UL clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A07G044
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bool "RZ/G2L clock support" if COMPILE_TEST
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select CLK_RZG2L
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@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
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This is a driver for R-Car USB2 clock selector
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config CLK_RZG2L
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bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
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bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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# Generic
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@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774A1_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
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DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC),
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DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1),
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@ -66,12 +66,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774B1_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -106,6 +102,9 @@ static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
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DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
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DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
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@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
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DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
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DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774C0_CLK_RPC),
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DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
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@ -108,6 +103,9 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
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DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
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DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC),
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DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074),
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DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078),
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DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c),
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@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A774E1_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -109,6 +105,9 @@ static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
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DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC),
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DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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DEF_FIXED("cp", R8A774E1_CLK_CP, CLK_EXTAL, 2, 1),
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@ -71,12 +71,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A7795_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -113,6 +109,9 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
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DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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@ -73,12 +73,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A7796_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -115,6 +111,9 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC),
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DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
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@ -69,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A77965_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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@ -110,6 +106,9 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
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DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268),
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DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c),
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DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC),
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DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
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DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
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@ -66,13 +66,10 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
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DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
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CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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R8A77980_CLK_RPC),
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DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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DEF_RATE(".oco", CLK_OCO, 32768),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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@ -99,6 +96,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
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DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074),
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DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074),
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DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
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DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC),
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||||
|
||||
DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
|
|
@ -74,6 +75,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
|
@ -107,6 +110,9 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c),
|
||||
|
||||
DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC),
|
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
|
@ -215,6 +221,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
|||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP),
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
|
|
@ -70,6 +71,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
|
@ -103,8 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
|
||||
DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268),
|
||||
|
||||
DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
|
@ -174,6 +180,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
|||
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2),
|
||||
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
|
||||
|
|
|
|||
|
|
@ -85,11 +85,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
|
||||
R8A779A0_CLK_RPC),
|
||||
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0),
|
||||
|
|
@ -120,6 +119,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
|
|||
DEF_GEN4_SDH("sdh0", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870),
|
||||
|
||||
DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
|
||||
R8A779A0_CLK_RPC),
|
||||
|
||||
DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
|
||||
|
|
|
|||
|
|
@ -70,12 +70,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
|
|||
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
|
||||
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
DEF_BASE(".rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
|
||||
|
|
@ -108,6 +107,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
|
|||
DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_GEN4_SD("sd0", R8A779F0_CLK_SD0, CLK_SDSRC, 0x870),
|
||||
|
||||
DEF_BASE("rpc", R8A779F0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A779F0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
|
||||
|
||||
DEF_DIV6P1("mso", R8A779F0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
|
||||
|
||||
DEF_GEN4_OSC("osc", R8A779F0_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
|
|
|||
220
drivers/clk/renesas/r9a07g043-cpg.c
Normal file
220
drivers/clk/renesas/r9a07g043-cpg.c
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* RZ/G2UL CPG driver
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/clock/r9a07g043-cpg.h>
|
||||
|
||||
#include "rzg2l-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_OSC_DIV1000,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL2_DIV2,
|
||||
CLK_PLL2_DIV2_8,
|
||||
CLK_PLL3,
|
||||
CLK_PLL3_DIV2,
|
||||
CLK_PLL3_DIV2_4,
|
||||
CLK_PLL3_DIV2_4_2,
|
||||
CLK_PLL5,
|
||||
CLK_PLL5_500,
|
||||
CLK_PLL5_250,
|
||||
CLK_PLL6,
|
||||
CLK_PLL6_250,
|
||||
CLK_P1_DIV2,
|
||||
CLK_PLL2_800,
|
||||
CLK_PLL2_SDHI_533,
|
||||
CLK_PLL2_SDHI_400,
|
||||
CLK_PLL2_SDHI_266,
|
||||
CLK_SD0_DIV4,
|
||||
CLK_SD1_DIV4,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
};
|
||||
|
||||
/* Divider tables */
|
||||
static const struct clk_div_table dtable_1_8[] = {
|
||||
{0, 1},
|
||||
{1, 2},
|
||||
{2, 4},
|
||||
{3, 8},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_1_32[] = {
|
||||
{0, 1},
|
||||
{1, 2},
|
||||
{2, 4},
|
||||
{3, 8},
|
||||
{4, 32},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
/* Mux clock tables */
|
||||
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
|
||||
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
|
||||
|
||||
static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
|
||||
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
|
||||
DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
|
||||
DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
|
||||
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
|
||||
DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
|
||||
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
|
||||
DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
|
||||
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
|
||||
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
|
||||
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
|
||||
CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
|
||||
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
|
||||
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
|
||||
DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
|
||||
DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
|
||||
DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
|
||||
DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
|
||||
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,
|
||||
sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
|
||||
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1,
|
||||
sel_shdi, ARRAY_SIZE(sel_shdi)),
|
||||
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
|
||||
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
|
||||
};
|
||||
|
||||
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
|
||||
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
|
||||
0x514, 0),
|
||||
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
|
||||
0x518, 0),
|
||||
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
|
||||
0x518, 1),
|
||||
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
|
||||
0x52c, 0),
|
||||
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
|
||||
0x52c, 1),
|
||||
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
|
||||
0x554, 0),
|
||||
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
|
||||
0x554, 1),
|
||||
DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
|
||||
0x554, 2),
|
||||
DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
|
||||
0x554, 3),
|
||||
DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
|
||||
0x554, 4),
|
||||
DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
|
||||
0x554, 5),
|
||||
DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
|
||||
0x554, 6),
|
||||
DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
|
||||
0x554, 7),
|
||||
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
|
||||
0x57c, 0),
|
||||
DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
|
||||
0x57c, 1),
|
||||
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
|
||||
0x57c, 1),
|
||||
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
|
||||
0x584, 0),
|
||||
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
|
||||
0x584, 1),
|
||||
DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
|
||||
0x584, 2),
|
||||
DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
|
||||
0x584, 3),
|
||||
DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
|
||||
0x584, 4),
|
||||
DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
|
||||
0x588, 0),
|
||||
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
|
||||
0x588, 1),
|
||||
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
|
||||
0x598, 0),
|
||||
};
|
||||
|
||||
static struct rzg2l_reset r9a07g043_resets[] = {
|
||||
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
|
||||
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
|
||||
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
|
||||
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
|
||||
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
|
||||
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
|
||||
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
|
||||
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
|
||||
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
|
||||
DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
||||
DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
|
||||
DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
|
||||
DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
|
||||
DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
|
||||
DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
|
||||
DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
|
||||
DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
|
||||
DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
|
||||
DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
|
||||
MOD_CLK_BASE + R9A07G043_IA55_CLK,
|
||||
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
|
||||
};
|
||||
|
||||
const struct rzg2l_cpg_info r9a07g043_cpg_info = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r9a07g043_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r9a07g043_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r9a07g043_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
|
||||
.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g043_resets,
|
||||
.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
|
||||
};
|
||||
|
|
@ -25,7 +25,7 @@ enum rcar_gen3_clk_types {
|
|||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
CLK_TYPE_GEN3_RPCSRC,
|
||||
CLK_TYPE_GEN3_E3_RPCSRC,
|
||||
CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_RPCD2,
|
||||
|
||||
|
|
@ -62,6 +62,9 @@ enum rcar_gen3_clk_types {
|
|||
#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
|
||||
(_parent0) << 16 | (_parent1), .div = 8)
|
||||
#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
|
||||
(_parent0) << 16 | (_parent1), .div = 5)
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
|
|
|
|||
|
|
@ -76,7 +76,6 @@ struct sd_hw_data {
|
|||
* @num_mod_clks: Number of Module Clocks in clks[]
|
||||
* @num_resets: Number of Module Resets in info->resets[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @notifiers: Notifier chain to save/restore clock state for system resume
|
||||
* @info: Pointer to platform data
|
||||
*/
|
||||
struct rzg2l_cpg_priv {
|
||||
|
|
@ -91,7 +90,6 @@ struct rzg2l_cpg_priv {
|
|||
unsigned int num_resets;
|
||||
unsigned int last_dt_core_clk;
|
||||
|
||||
struct raw_notifier_head notifiers;
|
||||
const struct rzg2l_cpg_info *info;
|
||||
};
|
||||
|
||||
|
|
@ -291,7 +289,7 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
|||
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
|
||||
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
|
||||
mult = MDIV(val1) + KDIV(val1) / 65536;
|
||||
div = PDIV(val1) * (1 << SDIV(val2));
|
||||
div = PDIV(val1) << SDIV(val2);
|
||||
|
||||
return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
|
||||
}
|
||||
|
|
@ -947,6 +945,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id rzg2l_cpg_match[] = {
|
||||
#ifdef CONFIG_CLK_R9A07G043
|
||||
{
|
||||
.compatible = "renesas,r9a07g043-cpg",
|
||||
.data = &r9a07g043_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A07G044
|
||||
{
|
||||
.compatible = "renesas,r9a07g044-cpg",
|
||||
|
|
|
|||
|
|
@ -202,6 +202,7 @@ struct rzg2l_cpg_info {
|
|||
unsigned int num_crit_mod_clks;
|
||||
};
|
||||
|
||||
extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
|
||||
|
||||
|
|
|
|||
184
include/dt-bindings/clock/r9a07g043-cpg.h
Normal file
184
include/dt-bindings/clock/r9a07g043-cpg.h
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2022 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R9A07G043 CPG Core Clocks */
|
||||
#define R9A07G043_CLK_I 0
|
||||
#define R9A07G043_CLK_I2 1
|
||||
#define R9A07G043_CLK_S0 2
|
||||
#define R9A07G043_CLK_SPI0 3
|
||||
#define R9A07G043_CLK_SPI1 4
|
||||
#define R9A07G043_CLK_SD0 5
|
||||
#define R9A07G043_CLK_SD1 6
|
||||
#define R9A07G043_CLK_M0 7
|
||||
#define R9A07G043_CLK_M2 8
|
||||
#define R9A07G043_CLK_M3 9
|
||||
#define R9A07G043_CLK_HP 10
|
||||
#define R9A07G043_CLK_TSU 11
|
||||
#define R9A07G043_CLK_ZT 12
|
||||
#define R9A07G043_CLK_P0 13
|
||||
#define R9A07G043_CLK_P1 14
|
||||
#define R9A07G043_CLK_P2 15
|
||||
#define R9A07G043_CLK_AT 16
|
||||
#define R9A07G043_OSCCLK 17
|
||||
#define R9A07G043_CLK_P0_DIV2 18
|
||||
|
||||
/* R9A07G043 Module Clocks */
|
||||
#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */
|
||||
#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */
|
||||
#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */
|
||||
#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */
|
||||
#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */
|
||||
#define R9A07G043_SYC_CNT_CLK 11
|
||||
#define R9A07G043_DMAC_ACLK 12
|
||||
#define R9A07G043_DMAC_PCLK 13
|
||||
#define R9A07G043_OSTM0_PCLK 14
|
||||
#define R9A07G043_OSTM1_PCLK 15
|
||||
#define R9A07G043_OSTM2_PCLK 16
|
||||
#define R9A07G043_MTU_X_MCK_MTU3 17
|
||||
#define R9A07G043_POE3_CLKM_POE 18
|
||||
#define R9A07G043_WDT0_PCLK 19
|
||||
#define R9A07G043_WDT0_CLK 20
|
||||
#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */
|
||||
#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */
|
||||
#define R9A07G043_SPI_CLK2 23
|
||||
#define R9A07G043_SPI_CLK 24
|
||||
#define R9A07G043_SDHI0_IMCLK 25
|
||||
#define R9A07G043_SDHI0_IMCLK2 26
|
||||
#define R9A07G043_SDHI0_CLK_HS 27
|
||||
#define R9A07G043_SDHI0_ACLK 28
|
||||
#define R9A07G043_SDHI1_IMCLK 29
|
||||
#define R9A07G043_SDHI1_IMCLK2 30
|
||||
#define R9A07G043_SDHI1_CLK_HS 31
|
||||
#define R9A07G043_SDHI1_ACLK 32
|
||||
#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */
|
||||
#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */
|
||||
#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */
|
||||
#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */
|
||||
#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */
|
||||
#define R9A07G043_SSI0_PCLK2 42
|
||||
#define R9A07G043_SSI0_PCLK_SFR 43
|
||||
#define R9A07G043_SSI1_PCLK2 44
|
||||
#define R9A07G043_SSI1_PCLK_SFR 45
|
||||
#define R9A07G043_SSI2_PCLK2 46
|
||||
#define R9A07G043_SSI2_PCLK_SFR 47
|
||||
#define R9A07G043_SSI3_PCLK2 48
|
||||
#define R9A07G043_SSI3_PCLK_SFR 49
|
||||
#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */
|
||||
#define R9A07G043_USB_U2H0_HCLK 51
|
||||
#define R9A07G043_USB_U2H1_HCLK 52
|
||||
#define R9A07G043_USB_U2P_EXR_CPUCLK 53
|
||||
#define R9A07G043_USB_PCLK 54
|
||||
#define R9A07G043_ETH0_CLK_AXI 55
|
||||
#define R9A07G043_ETH0_CLK_CHI 56
|
||||
#define R9A07G043_ETH1_CLK_AXI 57
|
||||
#define R9A07G043_ETH1_CLK_CHI 58
|
||||
#define R9A07G043_I2C0_PCLK 59
|
||||
#define R9A07G043_I2C1_PCLK 60
|
||||
#define R9A07G043_I2C2_PCLK 61
|
||||
#define R9A07G043_I2C3_PCLK 62
|
||||
#define R9A07G043_SCIF0_CLK_PCK 63
|
||||
#define R9A07G043_SCIF1_CLK_PCK 64
|
||||
#define R9A07G043_SCIF2_CLK_PCK 65
|
||||
#define R9A07G043_SCIF3_CLK_PCK 66
|
||||
#define R9A07G043_SCIF4_CLK_PCK 67
|
||||
#define R9A07G043_SCI0_CLKP 68
|
||||
#define R9A07G043_SCI1_CLKP 69
|
||||
#define R9A07G043_IRDA_CLKP 70
|
||||
#define R9A07G043_RSPI0_CLKB 71
|
||||
#define R9A07G043_RSPI1_CLKB 72
|
||||
#define R9A07G043_RSPI2_CLKB 73
|
||||
#define R9A07G043_CANFD_PCLK 74
|
||||
#define R9A07G043_GPIO_HCLK 75
|
||||
#define R9A07G043_ADC_ADCLK 76
|
||||
#define R9A07G043_ADC_PCLK 77
|
||||
#define R9A07G043_TSU_PCLK 78
|
||||
|
||||
/* R9A07G043 Resets */
|
||||
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */
|
||||
#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */
|
||||
#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */
|
||||
#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */
|
||||
#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */
|
||||
#define R9A07G043_DMAC_ARESETN 17
|
||||
#define R9A07G043_DMAC_RST_ASYNC 18
|
||||
#define R9A07G043_SYC_RESETN 19
|
||||
#define R9A07G043_OSTM0_PRESETZ 20
|
||||
#define R9A07G043_OSTM1_PRESETZ 21
|
||||
#define R9A07G043_OSTM2_PRESETZ 22
|
||||
#define R9A07G043_MTU_X_PRESET_MTU3 23
|
||||
#define R9A07G043_POE3_RST_M_REG 24
|
||||
#define R9A07G043_WDT0_PRESETN 25
|
||||
#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */
|
||||
#define R9A07G043_SPI_RST 27
|
||||
#define R9A07G043_SDHI0_IXRST 28
|
||||
#define R9A07G043_SDHI1_IXRST 29
|
||||
#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */
|
||||
#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */
|
||||
#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */
|
||||
#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */
|
||||
#define R9A07G043_SSI0_RST_M2_REG 36
|
||||
#define R9A07G043_SSI1_RST_M2_REG 37
|
||||
#define R9A07G043_SSI2_RST_M2_REG 38
|
||||
#define R9A07G043_SSI3_RST_M2_REG 39
|
||||
#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */
|
||||
#define R9A07G043_USB_U2H0_HRESETN 41
|
||||
#define R9A07G043_USB_U2H1_HRESETN 42
|
||||
#define R9A07G043_USB_U2P_EXL_SYSRST 43
|
||||
#define R9A07G043_USB_PRESETN 44
|
||||
#define R9A07G043_ETH0_RST_HW_N 45
|
||||
#define R9A07G043_ETH1_RST_HW_N 46
|
||||
#define R9A07G043_I2C0_MRST 47
|
||||
#define R9A07G043_I2C1_MRST 48
|
||||
#define R9A07G043_I2C2_MRST 49
|
||||
#define R9A07G043_I2C3_MRST 50
|
||||
#define R9A07G043_SCIF0_RST_SYSTEM_N 51
|
||||
#define R9A07G043_SCIF1_RST_SYSTEM_N 52
|
||||
#define R9A07G043_SCIF2_RST_SYSTEM_N 53
|
||||
#define R9A07G043_SCIF3_RST_SYSTEM_N 54
|
||||
#define R9A07G043_SCIF4_RST_SYSTEM_N 55
|
||||
#define R9A07G043_SCI0_RST 56
|
||||
#define R9A07G043_SCI1_RST 57
|
||||
#define R9A07G043_IRDA_RST 58
|
||||
#define R9A07G043_RSPI0_RST 59
|
||||
#define R9A07G043_RSPI1_RST 60
|
||||
#define R9A07G043_RSPI2_RST 61
|
||||
#define R9A07G043_CANFD_RSTP_N 62
|
||||
#define R9A07G043_CANFD_RSTC_N 63
|
||||
#define R9A07G043_GPIO_RSTN 64
|
||||
#define R9A07G043_GPIO_PORT_RESETN 65
|
||||
#define R9A07G043_GPIO_SPARE_RESETN 66
|
||||
#define R9A07G043_ADC_PRESETN 67
|
||||
#define R9A07G043_ADC_ADRST_N 68
|
||||
#define R9A07G043_TSU_PRESETN 69
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
|
||||
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Block a user