PCI: qcom: Rename qcom_pcie_set_slot_nccs() to qcom_pcie_set_slot_cap()

qcom_pcie_set_slot_nccs() currently only sets the NCCS field in the Slot
Capabilities register. A following patch adds programming of another
field in the same register, so rename the function to
qcom_pcie_set_slot_cap() to reflect that it configures Slot Capabilities
as a whole, not just NCCS.

No functional change intended.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260713-b4-clear_abp_0713-v2-1-4f0333a98d4e@oss.qualcomm.com
This commit is contained in:
Qiang Yu 2026-07-13 00:42:50 -07:00 committed by Manivannan Sadhasivam
parent 3edb3a038d
commit 9f46f9d696

View File

@ -358,7 +358,7 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
dw_pcie_dbi_ro_wr_dis(pci);
}
static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci)
static void qcom_pcie_set_slot_cap(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 val;
@ -580,7 +580,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
writel(CFG_BRIDGE_SB_INIT,
pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
qcom_pcie_set_slot_nccs(pcie->pci);
qcom_pcie_set_slot_cap(pcie->pci);
return 0;
}
@ -660,7 +660,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
}
qcom_pcie_set_slot_nccs(pcie->pci);
qcom_pcie_set_slot_cap(pcie->pci);
return 0;
}
@ -759,7 +759,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
val |= EN;
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
qcom_pcie_set_slot_nccs(pcie->pci);
qcom_pcie_set_slot_cap(pcie->pci);
return 0;
}
@ -1078,7 +1078,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
qcom_pcie_set_slot_nccs(pcie->pci);
qcom_pcie_set_slot_cap(pcie->pci);
return 0;
}