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PCI: rzg3s-host: Prepare System Controller handling for multiple controllers

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Prepare the driver to handle multiple PCIe controllers with distinct
System Controller (SYSC) register sets, as required by RZ/V2H(P). The
current design stores a single sysc_info structure per SoC, which is
insufficient for multi-controller configurations.

Introduce controller identifiers and extend struct rzg3s_pcie_soc_data
to hold a sysc_info array indexed per PCIe controller. Add a
controller_id field to struct rzg3s_pcie_host and select the appropriate
System Controller information during probe based on the hardware
instance.

Keep existing single-controller SoCs functionally unchanged while
preparing the driver for RZ/V2H(P) multi-controller support.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260629220932.861445-4-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar 2026-06-29 23:09:31 +01:00 committed by Manivannan Sadhasivam
parent e226045494
commit 9f2ed7c3de
1 changed files with 33 additions and 15 deletions
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48
drivers/pci/controller/pcie-rzg3s-host.c
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@ -242,6 +242,18 @@ struct rzg3s_pcie_msi {
int irq;
};
/**
* enum rzg3s_pcie_controller_id - RZ/G3S PCIe controller IDs
* @RZG3S_PCIE_CONTROLLER_ID_0: PCIe controller 0
* @RZG3S_PCIE_CONTROLLER_ID_1: PCIe controller 1
* @RZG3S_PCIE_CONTROLLER_ID_MAX: Max PCIe controllers
*/
enum rzg3s_pcie_controller_id {
RZG3S_PCIE_CONTROLLER_ID_0,
RZG3S_PCIE_CONTROLLER_ID_1,
RZG3S_PCIE_CONTROLLER_ID_MAX,
};
struct rzg3s_pcie_host;
/**
@ -254,7 +266,7 @@ struct rzg3s_pcie_host;
* power-on
* @cfg_resets: array with the resets that need to be de-asserted after
* configuration
* @sysc_info: SYSC info
* @sysc_info: System Controller info for each controller
* @num_power_resets: number of power resets
* @num_cfg_resets: number of configuration resets
*/
@ -265,7 +277,7 @@ struct rzg3s_pcie_soc_data {
int (*config_deinit)(struct rzg3s_pcie_host *host);
const char * const *power_resets;
const char * const *cfg_resets;
struct rzg3s_sysc_info sysc_info;
struct rzg3s_sysc_info sysc_info[RZG3S_PCIE_CONTROLLER_ID_MAX];
u8 num_power_resets;
u8 num_cfg_resets;
};
@ -297,6 +309,7 @@ struct rzg3s_pcie_port {
* @hw_lock: lock for access to the HW resources
* @intx_irqs: INTx interrupts
* @max_link_speed: maximum supported link speed
* @controller_id: PCIe controller identifier, used for System Controller access
*/
struct rzg3s_pcie_host {
void __iomem *axi;
@ -312,6 +325,7 @@ struct rzg3s_pcie_host {
raw_spinlock_t hw_lock;
int intx_irqs[PCI_NUM_INTX];
int max_link_speed;
enum rzg3s_pcie_controller_id controller_id;
};
#define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host, msi)
@ -1699,7 +1713,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)
return -ENOMEM;
sysc = host->sysc;
sysc->info = &host->data->sysc_info;
sysc->info = &host->data->sysc_info[host->controller_id];
host->axi = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(host->axi))
@ -1892,10 +1906,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {
.config_deinit = rzg3s_pcie_config_deinit,
.init_phy = rzg3s_soc_pcie_init_phy,
.sysc_info = {
.functions = {
[RZG3S_SYSC_FUNC_ID_RST_RSM_B] = {
.offset = 0xd74,
.mask = BIT(0),
[RZG3S_PCIE_CONTROLLER_ID_0] = {
.functions = {
[RZG3S_SYSC_FUNC_ID_RST_RSM_B] = {
.offset = 0xd74,
.mask = BIT(0),
},
},
},
},
@ -1910,14 +1926,16 @@ static const struct rzg3s_pcie_soc_data rzg3e_soc_data = {
.config_post_init = rzg3e_pcie_config_post_init,
.config_deinit = rzg3e_pcie_config_deinit,
.sysc_info = {
.functions = {
[RZG3S_SYSC_FUNC_ID_L1_ALLOW] = {
.offset = 0x1020,
.mask = BIT(0),
},
[RZG3S_SYSC_FUNC_ID_MODE] = {
.offset = 0x1024,
.mask = BIT(0),
[RZG3S_PCIE_CONTROLLER_ID_0] = {
.functions = {
[RZG3S_SYSC_FUNC_ID_L1_ALLOW] = {
.offset = 0x1020,
.mask = BIT(0),
},
[RZG3S_SYSC_FUNC_ID_MODE] = {
.offset = 0x1024,
.mask = BIT(0),
},
},
},
},