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media: cadence: csi2rx: Enable csi2rx_err_irq interrupt and add support for VIDIOC_LOG_STATUS
Enable the csi2rx_err_irq interrupt to record any errors during streaming and also add support for VIDIOC_LOG_STATUS ioctl. This allows users to retrieve detailed error information during streaming, including FIFO overflow, packet errors, and ECC errors. Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Reviewed-by: Changhuang Liang <changhuang.liang@starfivetech.com> Tested-by: Jai Luthra <jai.luthra@linux.dev> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
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@ -57,6 +57,25 @@
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#define CSI2RX_LANES_MAX 4
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#define CSI2RX_STREAMS_MAX 4
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#define CSI2RX_ERROR_IRQS_REG 0x28
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#define CSI2RX_ERROR_IRQS_MASK_REG 0x2C
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#define CSI2RX_STREAM3_FIFO_OVERFLOW_IRQ BIT(19)
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#define CSI2RX_STREAM2_FIFO_OVERFLOW_IRQ BIT(18)
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#define CSI2RX_STREAM1_FIFO_OVERFLOW_IRQ BIT(17)
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#define CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ BIT(16)
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#define CSI2RX_FRONT_TRUNC_HDR_IRQ BIT(12)
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#define CSI2RX_PROT_TRUNCATED_PACKET_IRQ BIT(11)
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#define CSI2RX_FRONT_LP_NO_PAYLOAD_IRQ BIT(10)
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#define CSI2RX_SP_INVALID_RCVD_IRQ BIT(9)
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#define CSI2RX_DATA_ID_IRQ BIT(7)
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#define CSI2RX_HEADER_CORRECTED_ECC_IRQ BIT(6)
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#define CSI2RX_HEADER_ECC_IRQ BIT(5)
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#define CSI2RX_PAYLOAD_CRC_IRQ BIT(4)
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#define CSI2RX_ECC_ERRORS GENMASK(7, 4)
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#define CSI2RX_PACKET_ERRORS GENMASK(12, 9)
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enum csi2rx_pads {
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CSI2RX_PAD_SINK,
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CSI2RX_PAD_SOURCE_STREAM0,
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@ -71,9 +90,32 @@ struct csi2rx_fmt {
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u8 bpp;
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};
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struct csi2rx_event {
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u32 mask;
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const char *name;
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};
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static const struct csi2rx_event csi2rx_events[] = {
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{ CSI2RX_STREAM3_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 3 FIFO detected" },
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{ CSI2RX_STREAM2_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 2 FIFO detected" },
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{ CSI2RX_STREAM1_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 1 FIFO detected" },
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{ CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 0 FIFO detected" },
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{ CSI2RX_FRONT_TRUNC_HDR_IRQ, "A truncated header [short or long] has been received" },
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{ CSI2RX_PROT_TRUNCATED_PACKET_IRQ, "A truncated long packet has been received" },
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{ CSI2RX_FRONT_LP_NO_PAYLOAD_IRQ, "A truncated long packet has been received. No payload" },
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{ CSI2RX_SP_INVALID_RCVD_IRQ, "A reserved or invalid short packet has been received" },
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{ CSI2RX_DATA_ID_IRQ, "Data ID error in the header packet" },
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{ CSI2RX_HEADER_CORRECTED_ECC_IRQ, "ECC error detected and corrected" },
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{ CSI2RX_HEADER_ECC_IRQ, "Unrecoverable ECC error" },
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{ CSI2RX_PAYLOAD_CRC_IRQ, "CRC error" },
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};
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#define CSI2RX_NUM_EVENTS ARRAY_SIZE(csi2rx_events)
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struct csi2rx_priv {
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struct device *dev;
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unsigned int count;
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int error_irq;
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/*
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* Used to prevent race conditions between multiple,
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@ -95,6 +137,7 @@ struct csi2rx_priv {
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u8 max_lanes;
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u8 max_streams;
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bool has_internal_dphy;
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u32 events[CSI2RX_NUM_EVENTS];
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struct v4l2_subdev subdev;
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struct v4l2_async_notifier notifier;
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@ -124,6 +167,54 @@ static const struct csi2rx_fmt formats[] = {
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{ .code = MEDIA_BUS_FMT_BGR888_1X24, .bpp = 24, },
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};
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static void csi2rx_configure_error_irq_mask(void __iomem *base,
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struct csi2rx_priv *csi2rx)
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{
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u32 error_irq_mask = 0;
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error_irq_mask |= CSI2RX_ECC_ERRORS;
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error_irq_mask |= CSI2RX_PACKET_ERRORS;
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/*
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* Iterate through all source pads and check if they are linked
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* to an active remote pad. If an active remote pad is found,
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* calculate the corresponding bit position and set it in
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* mask, enabling the stream overflow error in the mask.
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*/
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for (int i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) {
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struct media_pad *remote_pad;
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remote_pad = media_pad_remote_pad_first(&csi2rx->pads[i]);
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if (remote_pad) {
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int pad = i - CSI2RX_PAD_SOURCE_STREAM0;
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u32 bit_mask = CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ << pad;
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error_irq_mask |= bit_mask;
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}
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}
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writel(error_irq_mask, base + CSI2RX_ERROR_IRQS_MASK_REG);
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}
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static irqreturn_t csi2rx_irq_handler(int irq, void *dev_id)
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{
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struct csi2rx_priv *csi2rx = dev_id;
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int i;
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u32 error_status, error_mask;
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error_status = readl(csi2rx->base + CSI2RX_ERROR_IRQS_REG);
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error_mask = readl(csi2rx->base + CSI2RX_ERROR_IRQS_MASK_REG);
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for (i = 0; i < CSI2RX_NUM_EVENTS; i++)
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if ((error_status & csi2rx_events[i].mask) &&
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(error_mask & csi2rx_events[i].mask))
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csi2rx->events[i]++;
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writel(error_status, csi2rx->base + CSI2RX_ERROR_IRQS_REG);
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return IRQ_HANDLED;
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}
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static const struct csi2rx_fmt *csi2rx_get_fmt_by_code(u32 code)
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{
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unsigned int i;
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@ -220,6 +311,9 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx)
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reset_control_deassert(csi2rx->p_rst);
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csi2rx_reset(csi2rx);
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if (csi2rx->error_irq >= 0)
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csi2rx_configure_error_irq_mask(csi2rx->base, csi2rx);
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reg = csi2rx->num_lanes << 8;
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for (i = 0; i < csi2rx->num_lanes; i++) {
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reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]);
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@ -332,6 +426,8 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx)
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reset_control_assert(csi2rx->sys_rst);
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clk_disable_unprepare(csi2rx->sys_clk);
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writel(0, csi2rx->base + CSI2RX_ERROR_IRQS_MASK_REG);
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for (i = 0; i < csi2rx->max_streams; i++) {
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writel(CSI2RX_STREAM_CTRL_STOP,
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csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
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@ -363,6 +459,21 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx)
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}
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}
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static int csi2rx_log_status(struct v4l2_subdev *sd)
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{
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struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(sd);
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unsigned int i;
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for (i = 0; i < CSI2RX_NUM_EVENTS; i++) {
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if (csi2rx->events[i])
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dev_info(csi2rx->dev, "%s events: %d\n",
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csi2rx_events[i].name,
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csi2rx->events[i]);
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}
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return 0;
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}
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static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable)
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{
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struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev);
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@ -468,7 +579,12 @@ static const struct v4l2_subdev_video_ops csi2rx_video_ops = {
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.s_stream = csi2rx_s_stream,
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};
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static const struct v4l2_subdev_core_ops csi2rx_core_ops = {
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.log_status = csi2rx_log_status,
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};
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static const struct v4l2_subdev_ops csi2rx_subdev_ops = {
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.core = &csi2rx_core_ops,
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.video = &csi2rx_video_ops,
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.pad = &csi2rx_pad_ops,
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};
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@ -705,6 +821,21 @@ static int csi2rx_probe(struct platform_device *pdev)
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if (ret)
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goto err_cleanup;
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csi2rx->error_irq = platform_get_irq_byname_optional(pdev, "error_irq");
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if (csi2rx->error_irq < 0) {
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dev_dbg(csi2rx->dev, "Optional interrupt not defined, proceeding without it\n");
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} else {
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ret = devm_request_irq(csi2rx->dev, csi2rx->error_irq,
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csi2rx_irq_handler, 0,
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dev_name(&pdev->dev), csi2rx);
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if (ret) {
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dev_err(csi2rx->dev,
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"Unable to request interrupt: %d\n", ret);
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goto err_cleanup;
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}
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}
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ret = v4l2_subdev_init_finalize(&csi2rx->subdev);
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if (ret)
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goto err_cleanup;
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