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arm64: dts: qcom: ipq5332: Add PCIe related nodes
Add phy and controller nodes for pcie0_x1 and pcie1_x2. Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250317100029.881286-4-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Praveenkumar I
Bjorn Andersson
parent
c249a0b6a4
commit
9ef4554362
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@ -252,6 +252,46 @@ tsens: thermal-sensor@4a9000 {
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#thermal-sensor-cells = <1>;
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};
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pcie0_phy: phy@4b0000 {
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compatible = "qcom,ipq5332-uniphy-pcie-phy";
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reg = <0x004b0000 0x800>;
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clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
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<&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
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resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
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<&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
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<&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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num-lanes = <1>;
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status = "disabled";
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};
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pcie1_phy: phy@4b1000 {
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compatible = "qcom,ipq5332-uniphy-pcie-phy";
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reg = <0x004b1000 0x1000>;
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clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
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<&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
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resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
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<&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>,
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<&gcc GCC_PCIE3X2PHY_PHY_BCR>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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num-lanes = <2>;
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5332-tlmm";
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reg = <0x01000000 0x300000>;
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@ -278,8 +318,8 @@ gcc: clock-controller@1800000 {
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#interconnect-cells = <1>;
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clocks = <&xo_board>,
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<&sleep_clk>,
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<0>,
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<0>,
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<&pcie1_phy>,
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<&pcie0_phy>,
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<0>;
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};
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@ -545,6 +585,214 @@ frame@b128000 {
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status = "disabled";
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};
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};
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pcie1: pcie@18000000 {
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compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
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reg = <0x18000000 0xf1c>,
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<0x18000f20 0xa8>,
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<0x18001000 0x1000>,
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<0x00088000 0x3000>,
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<0x18100000 0x1000>,
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<0x0008b000 0x1000>;
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reg-names = "dbi",
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"elbi",
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"atu",
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"parf",
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"config",
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"mhi";
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device_type = "pci";
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linux,pci-domain = <1>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x00100000>,
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<0x02000000 0x0 0x18300000 0x18300000 0x0 0x07d00000>;
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msi-map = <0x0 &v2m0 0x0 0xffd>;
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interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>,
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<&gcc GCC_PCIE3X2_AXI_S_CLK>,
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<&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
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<&gcc GCC_PCIE3X2_RCHG_CLK>,
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<&gcc GCC_PCIE3X2_AHB_CLK>,
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<&gcc GCC_PCIE3X2_AUX_CLK>;
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clock-names = "axi_m",
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"axi_s",
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"axi_bridge",
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"rchng",
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"ahb",
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"aux";
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assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>;
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assigned-clock-rates = <2000000>;
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resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
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<&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
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<&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
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<&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
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<&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
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<&gcc GCC_PCIE3X2_AUX_CLK_ARES>,
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<&gcc GCC_PCIE3X2_AHB_CLK_ARES>;
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reset-names = "pipe",
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"sticky",
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"axi_s_sticky",
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"axi_s",
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"axi_m_sticky",
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"axi_m",
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"aux",
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"ahb";
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>,
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<&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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status = "disabled";
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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pcie0: pcie@20000000 {
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compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
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reg = <0x20000000 0xf1c>,
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<0x20000f20 0xa8>,
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<0x20001000 0x1000>,
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<0x00080000 0x3000>,
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<0x20100000 0x1000>,
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<0x00083000 0x1000>;
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reg-names = "dbi",
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"elbi",
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"atu",
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"parf",
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"config",
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"mhi";
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x00100000>,
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<0x02000000 0x0 0x20300000 0x20300000 0x0 0x0fd00000>;
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msi-map = <0x0 &v2m0 0x0 0xffd>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
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<&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
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<&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
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<&gcc GCC_PCIE3X1_0_RCHG_CLK>,
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<&gcc GCC_PCIE3X1_0_AHB_CLK>,
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<&gcc GCC_PCIE3X1_0_AUX_CLK>;
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clock-names = "axi_m",
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"axi_s",
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"axi_bridge",
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"rchng",
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"ahb",
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"aux";
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assigned-clocks = <&gcc GCC_PCIE3X1_0_AUX_CLK>;
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assigned-clock-rates = <2000000>;
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resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
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<&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
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<&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
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<&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
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<&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
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<&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>,
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<&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>;
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reset-names = "pipe",
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"sticky",
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"axi_s_sticky",
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"axi_s",
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"axi_m_sticky",
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"axi_m",
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"aux",
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"ahb";
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>,
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<&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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status = "disabled";
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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};
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thermal-zones {
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