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arm64: dts: apple: s5l8960x: Add cpufreq nodes

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Add cpufreq nodes for Apple A7 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Nick Chan 2025-02-03 20:43:40 +08:00 committed by Sven Peter
parent 68795d7ab0
commit 9e908d5f24
6 changed files with 103 additions and 0 deletions
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1
arch/arm64/boot/dts/apple/s5l8960x-5s.dtsi
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@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
#include "s5l8960x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {

1
arch/arm64/boot/dts/apple/s5l8960x-air1.dtsi
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@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
#include "s5l8965x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {

1
arch/arm64/boot/dts/apple/s5l8960x-mini2.dtsi
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@ -8,6 +8,7 @@
#include "s5l8960x.dtsi"
#include "s5l8960x-common.dtsi"
#include "s5l8960x-opp.dtsi"
#include <dt-bindings/input/input.h>
/ {

45
arch/arm64/boot/dts/apple/s5l8960x-opp.dtsi Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz
*
* target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m
*
* Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com>
*/
/ {
cyclone_opp: opp-table {
compatible = "operating-points-v2";
opp01 {
opp-hz = /bits/ 64 <300000000>;
opp-level = <1>;
clock-latency-ns = <15500>;
};
opp02 {
opp-hz = /bits/ 64 <396000000>;
opp-level = <2>;
clock-latency-ns = <43000>;
};
opp03 {
opp-hz = /bits/ 64 <600000000>;
opp-level = <3>;
clock-latency-ns = <26000>;
};
opp04 {
opp-hz = /bits/ 64 <840000000>;
opp-level = <4>;
clock-latency-ns = <30000>;
};
opp05 {
opp-hz = /bits/ 64 <1128000000>;
opp-level = <5>;
clock-latency-ns = <39500>;
};
opp06 {
opp-hz = /bits/ 64 <1296000000>;
opp-level = <6>;
clock-latency-ns = <45500>;
};
};
};

10
arch/arm64/boot/dts/apple/s5l8960x.dtsi
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@ -33,6 +33,8 @@ cpu0: cpu@0 {
compatible = "apple,cyclone";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&cyclone_opp>;
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@ -41,6 +43,8 @@ cpu1: cpu@1 {
compatible = "apple,cyclone";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
operating-points-v2 = <&cyclone_opp>;
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@ -53,6 +57,12 @@ soc {
nonposted-mmio;
ranges;
cpufreq: performance-controller@202220000 {
compatible = "apple,s5l8960x-cluster-cpufreq";
reg = <0x2 0x02220000 0 0x1000>;
#performance-domain-cells = <0>;
};
serial0: serial@20a0a0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0a0000 0x0 0x4000>;

45
arch/arm64/boot/dts/apple/s5l8965x-opp.dtsi Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz
*
* target-type: J71, J72, J73
*
* Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com>
*/
/ {
cyclone_opp: opp-table {
compatible = "operating-points-v2";
opp01 {
opp-hz = /bits/ 64 <300000000>;
opp-level = <1>;
clock-latency-ns = <10000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-level = <2>;
clock-latency-ns = <49000>;
};
opp03 {
opp-hz = /bits/ 64 <840000000>;
opp-level = <3>;
clock-latency-ns = <30000>;
};
opp04 {
opp-hz = /bits/ 64 <1128000000>;
opp-level = <4>;
clock-latency-ns = <39500>;
};
opp05 {
opp-hz = /bits/ 64 <1296000000>;
opp-level = <5>;
clock-latency-ns = <45500>;
};
opp06 {
opp-hz = /bits/ 64 <1392000000>;
opp-level = <6>;
clock-latency-ns = <46500>;
};
};
};