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drm/xe: Apply WA_14026999295 to engine

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Apply WA_14026999295 to following IPs:
Xe3p_XPC

v2:
- Move WA to "Xe3p_XPC" section at bottom of table. (Matt)

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Link: https://patch.msgid.link/20260327102414.780515-2-mallesh.koujalagi@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Mallesh Koujalagi 2026-03-27 15:54:15 +05:30 committed by Matt Roper
parent d0672008cd
commit 9e7585fb70
2 changed files with 9 additions and 0 deletions
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1
drivers/gpu/drm/xe/regs/xe_gt_regs.h
View File

@ -528,6 +528,7 @@
#define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
#define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14)
#define DIS_EU_GRF_POISON_TO_LSC REG_BIT(13)
#define DIS_FIX_EOT1_FLUSH REG_BIT(9)
#define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)

8
drivers/gpu/drm/xe/xe_wa.c
View File

@ -601,6 +601,14 @@ static const struct xe_rtp_entry_sr engine_was[] = {
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
},
/* Xe3p_XPC */
{ XE_RTP_NAME("14026999295"),
XE_RTP_RULES(GRAPHICS_VERSION(3511),
FUNC(xe_rtp_match_first_render_or_compute)),
XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_EU_GRF_POISON_TO_LSC))
},
};
static const struct xe_rtp_entry_sr lrc_was[] = {