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riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property

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RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent
property to RZ/Five SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2023-09-29 01:07:01 +01:00 committed by Geert Uytterhoeven
parent a38b1061d3
commit 9e40584dc2
1 changed files with 1 additions and 0 deletions
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arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
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@ -43,6 +43,7 @@ cpu0_intc: interrupt-controller {
};
&soc {
dma-noncoherent;
interrupt-parent = <&plic>;
plic: interrupt-controller@12c00000 {