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drm/amdgpu/mes: centralize gfx_hqd mask management

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Move it to amdgpu_mes to align with the compute and
sdma hqd masks. No functional change.

v2: rebase on new changes
v3: misc optimizations

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Sunil Khatri<sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2025-02-26 12:31:46 -05:00
parent 4220d2c7c4
commit 9e2bbba1d5
3 changed files with 27 additions and 25 deletions
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21
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
View File

@ -108,6 +108,27 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
adev->mes.vmid_mask_mmhub = 0xffffff00;
adev->mes.vmid_mask_gfxhub = 0xffffff00;
for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) {
if (i >= adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me)
break;
if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
IP_VERSION(12, 0, 0))
/*
* GFX V12 has only one GFX pipe, but 8 queues in it.
* GFX pipe 0 queue 0 is being used by Kernel queue.
* Set GFX pipe 0 queue 1-7 for MES scheduling
* mask = 1111 1110b
*/
adev->mes.gfx_hqd_mask[i] = 0xFE;
else
/*
* GFX pipe 0 queue 0 is being used by Kernel queue.
* Set GFX pipe 0 queue 1 for MES scheduling
* mask = 10b
*/
adev->mes.gfx_hqd_mask[i] = 0x2;
}
for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec))
break;

16
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
View File

@ -669,18 +669,6 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
offsetof(union MESAPI__MISC, api_status));
}
static void mes_v11_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
{
/*
* GFX pipe 0 queue 0 is being used by Kernel queue.
* Set GFX pipe 0 queue 1 for MES scheduling
* mask = 10b
* GFX pipe 1 can't be used for MES due to HW limitation.
*/
pkt->gfx_hqd_mask[0] = 0x2;
pkt->gfx_hqd_mask[1] = 0;
}
static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
{
int i;
@ -705,7 +693,9 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
mes_set_hw_res_pkt.compute_hqd_mask[i] =
mes->compute_hqd_mask[i];
mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
for (i = 0; i < MAX_GFX_PIPES; i++)
mes_set_hw_res_pkt.gfx_hqd_mask[i] =
mes->gfx_hqd_mask[i];
for (i = 0; i < MAX_SDMA_PIPES; i++)
mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];

15
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
View File

@ -694,17 +694,6 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
}
static void mes_v12_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
{
/*
* GFX V12 has only one GFX pipe, but 8 queues in it.
* GFX pipe 0 queue 0 is being used by Kernel queue.
* Set GFX pipe 0 queue 1-7 for MES scheduling
* mask = 1111 1110b
*/
pkt->gfx_hqd_mask[0] = 0xFE;
}
static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
{
int i;
@ -727,7 +716,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
mes_set_hw_res_pkt.compute_hqd_mask[i] =
mes->compute_hqd_mask[i];
mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
for (i = 0; i < MAX_GFX_PIPES; i++)
mes_set_hw_res_pkt.gfx_hqd_mask[i] =
mes->gfx_hqd_mask[i];
for (i = 0; i < MAX_SDMA_PIPES; i++)
mes_set_hw_res_pkt.sdma_hqd_mask[i] =