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amd-xgbe: add support for giant packet size

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AMD XGBE hardware supports giant Ethernet frames up to 16K bytes.
Add support for configuring and enabling giant packet handling
in the driver.

- Define new register fields and macros for giant packet support.
- Update the jumbo frame configuration logic to enable giant
  packet mode when MTU exceeds the jumbo threshold.

Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250701121929.319690-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Raju Rangoju 2025-07-01 17:49:29 +05:30 committed by Jakub Kicinski
parent 7d2dabaa17
commit 9e2a7ad4ae
4 changed files with 24 additions and 4 deletions
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8
drivers/net/ethernet/amd/xgbe/xgbe-common.h
View File

@ -364,6 +364,10 @@
#define MAC_RCR_CST_WIDTH 1
#define MAC_RCR_DCRCC_INDEX 3
#define MAC_RCR_DCRCC_WIDTH 1
#define MAC_RCR_GPSLCE_INDEX 6
#define MAC_RCR_GPSLCE_WIDTH 1
#define MAC_RCR_WD_INDEX 7
#define MAC_RCR_WD_WIDTH 1
#define MAC_RCR_HDSMS_INDEX 12
#define MAC_RCR_HDSMS_WIDTH 3
#define MAC_RCR_IPC_INDEX 9
@ -374,6 +378,8 @@
#define MAC_RCR_LM_WIDTH 1
#define MAC_RCR_RE_INDEX 0
#define MAC_RCR_RE_WIDTH 1
#define MAC_RCR_GPSL_INDEX 16
#define MAC_RCR_GPSL_WIDTH 14
#define MAC_RFCR_PFCE_INDEX 8
#define MAC_RFCR_PFCE_WIDTH 1
#define MAC_RFCR_RFE_INDEX 0
@ -412,6 +418,8 @@
#define MAC_TCR_VNE_WIDTH 1
#define MAC_TCR_VNM_INDEX 25
#define MAC_TCR_VNM_WIDTH 1
#define MAC_TCR_JD_INDEX 16
#define MAC_TCR_JD_WIDTH 1
#define MAC_TIR_TNID_INDEX 0
#define MAC_TIR_TNID_WIDTH 16
#define MAC_TSCR_AV8021ASMEN_INDEX 28

16
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
View File

@ -2850,9 +2850,19 @@ static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
{
unsigned int val;
val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
if (pdata->netdev->mtu > XGMAC_JUMBO_PACKET_MTU) {
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSL,
XGMAC_GIANT_PACKET_MTU);
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 1);
XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 1);
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 1);
} else {
val = pdata->netdev->mtu > XGMAC_STD_PACKET_MTU ? 1 : 0;
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 0);
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 0);
XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 0);
XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
}
}
static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)

2
drivers/net/ethernet/amd/xgbe/xgbe-main.c
View File

@ -275,7 +275,7 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
netdev->priv_flags |= IFF_UNICAST_FLT;
netdev->min_mtu = 0;
netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU;
netdev->max_mtu = XGMAC_GIANT_PACKET_MTU - XGBE_ETH_FRAME_HDR;
/* Use default watchdog timeout */
netdev->watchdog_timeo = 0;

2
drivers/net/ethernet/amd/xgbe/xgbe.h
View File

@ -80,11 +80,13 @@
#define XGBE_IRQ_MODE_EDGE 0
#define XGBE_IRQ_MODE_LEVEL 1
#define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
#define XGMAC_MIN_PACKET 60
#define XGMAC_STD_PACKET_MTU 1500
#define XGMAC_MAX_STD_PACKET 1518
#define XGMAC_JUMBO_PACKET_MTU 9000
#define XGMAC_MAX_JUMBO_PACKET 9018
#define XGMAC_GIANT_PACKET_MTU 16368
#define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
#define XGMAC_PFC_DATA_LEN 46