diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index ad144c02eb7e..c6af3a46364f 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -183,10 +183,12 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 - - description: Phytec STM32MP1 SoM based Boards + - description: Phytec STM32MP157 SoM based Boards items: - - const: phytec,phycore-stm32mp1-3 - - const: phytec,phycore-stm32mp157c-som + - enum: + - phytec,phycore-stm32mp1-3 # phyBOARD-Sargas with phyCORE-STM32MP157C SoM + - enum: + - phytec,phycore-stm32mp157c-som # phyCORE-STM32MP157C SoM - const: st,stm32mp157 - description: Ultratronik STM32MP1 SBC based Boards diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index e906bf6ba004..10c5d75f6169 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -16,6 +16,91 @@ dtb-$(CONFIG_ARCH_STI) += \ stih410-b2260.dtb \ stih418-b2199.dtb \ stih418-b2264.dtb + +stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2-dtbs := \ + stm32mp135f-dhcor-dhsbc.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo + +stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo + +stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo + +stm32mp15xx-avenger96-overlay-fdcan1-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo + +stm32mp15xx-avenger96-overlay-fdcan2-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo + +stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo + +stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo + +stm32mp15xx-avenger96-overlay-ov5640-x7-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo + +stm32mp15xx-avenger96-overlay-spi2-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo + +stm32mp15xx-dhcom-drc02-overlay-wifi-rsi-dtbs := \ + stm32mp153c-dhcom-drc02.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo + +stm32mp15xx-dhcom-pdk2-overlay-460-200-x11-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-497-200-x12-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-531-100-x21-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-531-100-x22-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-560-200-x12-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-672-100-x18-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6-dtbs := \ + stm32mp157c-dhcom-picoitx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \ + dtb-$(CONFIG_ARCH_STM32) += \ stm32f429-disco.dtb \ stm32f469-disco.dtb \ @@ -30,6 +115,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h750i-art-pi.dtb \ stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ @@ -39,12 +126,30 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151c-mect1s.dtb \ stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp153c-lxa-fairytux2-gen1.dtb \ stm32mp153c-lxa-fairytux2-gen2.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtb \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtb \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtb \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ stm32mp157a-dk1-scmi.dtb \ @@ -56,7 +161,29 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \ stm32mp157c-dhcom-picoitx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \ stm32mp157c-dk2.dtb \ stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ @@ -69,7 +196,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb \ + stm32mp157c-phyboard-sargas-rdk.dtb \ stm32mp157c-ultra-fly-sbc.dtb \ stm32mp157f-dk2.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index b9657ff91c23..83ae59b73dd0 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ +#include #include #include #include @@ -469,8 +470,8 @@ i2c1: i2c@40012000 { compatible = "st,stm32mp13-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C1_K>; resets = <&rcc I2C1_R>; #address-cells = <1>; @@ -478,6 +479,7 @@ i2c1: i2c@40012000 { dmas = <&dmamux1 33 0x400 0x1>, <&dmamux1 34 0x400 0x1>; dma-names = "rx", "tx"; + wakeup-source; st,syscfg-fmp = <&syscfg 0x4 0x1>; i2c-analog-filter; status = "disabled"; @@ -487,8 +489,8 @@ i2c2: i2c@40013000 { compatible = "st,stm32mp13-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C2_K>; resets = <&rcc I2C2_R>; #address-cells = <1>; @@ -497,6 +499,7 @@ i2c2: i2c@40013000 { <&dmamux1 36 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; i2c-analog-filter; status = "disabled"; }; @@ -964,9 +967,125 @@ hdp: pinctrl@5002a000 { compatible = "st,stm32mp131-hdp"; reg = <0x5002a000 0x400>; clocks = <&rcc HDP>; + access-controllers = <&dbg_bus 1>; status = "disabled"; }; + dbg_bus: bus@50080000 { + compatible = "st,stm32mp131-dbg-bus"; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges = <0x50080000 0x50080000 0x3f80000>; + status = "disabled"; + + cs_etf: etf@50092000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x50092000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x50093000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x50094000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d8000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dc000 0x1000>; + cpu = <&cpu0>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -1129,7 +1248,7 @@ usart1: serial@4c000000 { resets = <&rcc USART1_R>; wakeup-source; dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; + <&dmamux1 42 0x400 0x1>; dma-names = "rx", "tx"; access-controllers = <&etzpc 16>; status = "disabled"; @@ -1143,7 +1262,7 @@ usart2: serial@4c001000 { resets = <&rcc USART2_R>; wakeup-source; dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; + <&dmamux1 44 0x400 0x1>; dma-names = "rx", "tx"; access-controllers = <&etzpc 17>; status = "disabled"; @@ -1155,7 +1274,7 @@ i2s4: audio-controller@4c002000 { #sound-dai-cells = <0>; interrupts = ; dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; + <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; access-controllers = <&etzpc 13>; status = "disabled"; @@ -1195,8 +1314,8 @@ i2c3: i2c@4c004000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c004000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C3_K>; resets = <&rcc I2C3_R>; #address-cells = <1>; @@ -1205,6 +1324,7 @@ i2c3: i2c@4c004000 { <&dmamux1 74 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 20>; status = "disabled"; @@ -1214,8 +1334,8 @@ i2c4: i2c@4c005000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c005000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C4_K>; resets = <&rcc I2C4_R>; #address-cells = <1>; @@ -1224,6 +1344,7 @@ i2c4: i2c@4c005000 { <&dmamux1 76 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 21>; status = "disabled"; @@ -1233,8 +1354,8 @@ i2c5: i2c@4c006000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c006000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C5_K>; resets = <&rcc I2C5_R>; #address-cells = <1>; @@ -1243,6 +1364,7 @@ i2c5: i2c@4c006000 { <&dmamux1 116 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 22>; status = "disabled"; @@ -1348,9 +1470,9 @@ timers15: timer@4c00a000 { clocks = <&rcc TIM15_K>; clock-names = "int"; dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; access-controllers = <&etzpc 26>; status = "disabled"; @@ -1383,7 +1505,7 @@ timers16: timer@4c00b000 { clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; + <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 27>; status = "disabled"; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 8dcf68b212b4..4d4cec8b86ac 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -187,6 +187,30 @@ &cryp { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dcmipp { pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcmipp_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso new file mode 100644 index 000000000000..3801dab141e8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + + button-1 { + label = "KEY2"; + linux,code = ; + gpios = <&gpiog 10 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + button-0 { + label = "KEY1"; + linux,code = ; + /* IRQ bank A shared with PA1 touch controller */ + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + + button-2 { + label = "KEY3"; + linux,code = ; + /* IRQ line 0 taken by PI0 / SoM RTC IRQ */ + gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&m_can1 { + /* Collides with KEY2/PG10 KEY3/PD0 */ + status = "disabled"; +}; + +&m_can2 { + /* Collides with TP_CS/PE6 */ + status = "disabled"; +}; + +&usart2 { + /* Collides with TP_IRQ/PA1 */ + status = "disabled"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpiof 3 0>, <&gpioe 0 0>; + status = "okay"; + + lcd@0 { + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <0>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + rotation = <90>; + }; + + tp@1 { + compatible = "ti,tsc2046"; + reg = <1>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <500000>; + ti,pressure-max = /bits/ 16 <255>; + ti,x-plate-ohms = /bits/ 16 <60>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 8613a6a17ee9..aaa91b634c12 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -231,6 +231,45 @@ pins { }; }; + /omit-if-no-ref/ + dcmi_pins_d: dcmi-3 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + dcmi_sleep_pins_d: dcmi-sleep-3 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + /omit-if-no-ref/ ethernet0_rgmii_pins_a: rgmii-0 { pins1 { @@ -394,6 +433,7 @@ pins1 { ethernet0_rgmii_pins_d: rgmii-3 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ @@ -1343,6 +1383,65 @@ pins { }; }; + /omit-if-no-ref/ + ltdc_pins_f: ltdc-5 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_f: ltdc-sleep-5 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ mco1_pins_a: mco1-0 { pins { @@ -1683,6 +1782,23 @@ pins { }; }; + /omit-if-no-ref/ + pwm5_pins_c: pwm5-2 { + pins { + pinmux = ; /* TIM5_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm5_sleep_pins_c: pwm5-sleep-2 { + pins { + pinmux = ; /* TIM5_CH4 */ + }; + }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { @@ -1908,6 +2024,21 @@ pins { }; }; + /omit-if-no-ref/ + sai2a_pins_d: sai2a-3 { + pins { + pinmux = ; /* SAI2_SD_A */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + sai2a_sleep_pins_d: sai2a-3 { + pins { + pinmux = ; /* SAI2_SD_A */ + }; + }; + /omit-if-no-ref/ sai2b_pins_a: sai2b-0 { pins1 { @@ -2895,6 +3026,39 @@ pins { }; }; + /omit-if-no-ref/ + uart4_pins_f: uart4-5 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_f: uart4-idle-5 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_f: uart4-sleep-5 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b1b568dfd126..84f68e8563d8 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ +#include #include #include #include @@ -123,6 +124,14 @@ soc { interrupt-parent = <&intc>; ranges; + sram4: sram@10050000 { + compatible = "mmio-sram"; + reg = <0x10050000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10050000 0x10000>; + }; + ipcc: mailbox@4c001000 { compatible = "st,stm32mp1-ipcc"; #mbox-cells = <1>; @@ -274,9 +283,180 @@ hdp: pinctrl@5002a000 { compatible = "st,stm32mp151-hdp"; reg = <0x5002a000 0x400>; clocks = <&rcc HDP>; + access-controllers = <&dbg_bus 1>; status = "disabled"; }; + dbg_bus: bus@50080000 { + compatible = "st,stm32mp151-dbg-bus"; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges = <0x50080000 0x50080000 0x3f80000>, + <0x90000000 0x90000000 0x1000000>; + status = "disabled"; + + cs_funnel: funnel@50091000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x50091000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&stm_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + }; + + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + cs_etf: etf@50092000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x50092000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x50093000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x50094000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + }; + + cs_stm: stm@500a0000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x500a0000 0x00001000>, + <0x90000000 0x01000000>; + reg-names = "stm-base", "stm-stimulus-base"; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d8000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dc000 0x1000>; + cpu = <&cpu0>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -867,12 +1047,15 @@ i2c1: i2c@40012000 { compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C1_K>; resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; i2c-analog-filter; @@ -884,12 +1067,15 @@ i2c2: i2c@40013000 { compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C2_K>; resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; i2c-analog-filter; @@ -901,12 +1087,15 @@ i2c3: i2c@40014000 { compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C3_K>; resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; i2c-analog-filter; @@ -918,12 +1107,15 @@ i2c5: i2c@40015000 { compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C5_K>; resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; i2c-analog-filter; @@ -1083,7 +1275,7 @@ usart6: serial@44003000 { clocks = <&rcc USART6_K>; wakeup-source; dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; + <&dmamux1 72 0x400 0x11>; dma-names = "rx", "tx"; access-controllers = <&etzpc 51>; status = "disabled"; @@ -1095,7 +1287,7 @@ i2s1: audio-controller@44004000 { reg = <0x44004000 0x400>; interrupts = ; dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; + <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; access-controllers = <&etzpc 52>; status = "disabled"; @@ -1110,7 +1302,7 @@ spi1: spi@44004000 { clocks = <&rcc SPI1_K>; resets = <&rcc SPI1_R>; dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; + <&dmamux1 38 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 52>; status = "disabled"; @@ -1125,7 +1317,7 @@ spi4: spi@44005000 { clocks = <&rcc SPI4_K>; resets = <&rcc SPI4_R>; dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; + <&dmamux1 84 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 53>; status = "disabled"; @@ -1176,7 +1368,7 @@ timers16: timer@44007000 { clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; + <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 55>; status = "disabled"; @@ -1209,7 +1401,7 @@ timers17: timer@44008000 { clocks = <&rcc TIM17_K>; clock-names = "int"; dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; + <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 56>; status = "disabled"; @@ -1241,7 +1433,7 @@ spi5: spi@44009000 { clocks = <&rcc SPI5_K>; resets = <&rcc SPI5_R>; dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; + <&dmamux1 86 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 57>; status = "disabled"; @@ -1829,12 +2021,15 @@ i2c4: i2c@5c002000 { compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C4_K>; resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, + <&mdma1 37 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; i2c-analog-filter; @@ -1846,12 +2041,15 @@ i2c6: i2c@5c009000 { compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C6_K>; resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 38 0x0 0x40008 0x0 0x0>, + <&mdma1 39 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; i2c-analog-filter; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 92794b942ab2..17d52d93695e 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -30,6 +30,74 @@ timer { }; }; +&cs_funnel { + in-ports { + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; +}; + +&dbg_bus { + cs_cti_cpu1: cti@500d9000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d9000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu1>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm1>; + }; + }; + + cs_etm1: etm@500dd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dd000 0x1000>; + cpu = <&cpu1>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + }; +}; + &etzpc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 4e46d58bf61f..0e65a1862eb5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -81,11 +81,59 @@ &cec { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dcmi { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcmi_pins_a>; pinctrl-1 = <&dcmi_sleep_pins_a>; + /* + * Enable DMA-MDMA chaining by adding a SRAM pool and + * a MDMA channel + */ + sram = <&dcmi_pool>; + + dmas = <&dmamux1 75 0x400 0x01>, <&mdma1 0 0x3 0x1200000a 0 0>; + dma-names = "tx", "mdma_tx"; port { dcmi_0: endpoint { @@ -171,6 +219,8 @@ &i2c2 { pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; ov5640: camera@3c { @@ -227,6 +277,8 @@ &i2c5 { pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -302,6 +354,13 @@ &spi1 { status = "disabled"; }; +&sram4 { + dcmi_pool: dcmi-sram@0 { + reg = <0x0 0x8000>; + pool; + }; +}; + &timers2 { /* spare dmas for other usage (un-delete to enable pwm capture) */ /delete-property/dmas; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts similarity index 58% rename from arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts rename to arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index 28d7203264ce..c18a37266083 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -6,39 +6,21 @@ /dts-v1/; -#include #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp157c-phycore-stm32mp15-som.dtsi" +#include "stm32mp15xx-phycore-som.dtsi" +#include "stm32mp15xx-phyboard-sargas.dtsi" / { - model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + model = "PHYTEC phyBOARD-Sargas STM32MP157C"; compatible = "phytec,phycore-stm32mp1-3", "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; - - aliases { - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - mmc2 = &sdmmc3; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &usart1; - }; }; &cryp1 { status = "okay"; }; -&dts { - status = "okay"; -}; - -&fmc { - status = "disabled"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso new file mode 100644 index 000000000000..103a2f0cf57b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +#include + +/dts-v1/; +/plugin/; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + phy-dsi-supply = <®18>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +<dc { + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso new file mode 100644 index 000000000000..cde2f8f68f86 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: touchscreen@38 { + }; + + attiny: regulator@45 { + }; +}; + +#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi" + +<dc { + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso new file mode 100644 index 000000000000..a9916aa8df75 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso new file mode 100644 index 000000000000..c994ff055227 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso new file mode 100644 index 000000000000..1edfff973a81 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso new file mode 100644 index 000000000000..bb3db38e3e63 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso new file mode 100644 index 000000000000..3056be6cd196 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + camera0_1v5_pwr: regulator-camera0-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v5-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + camera0_1v8_pwr: regulator-camera0-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v8-reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera0_2v8_pwr: regulator-camera0-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-2v8-reg"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&dcmi { + status = "okay"; +}; + +&dcmi_0 { + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + AVDD-supply = <&camera0_2v8_pwr>; + DOVDD-supply = <&camera0_1v8_pwr>; + DVDD-supply = <&camera0_1v5_pwr>; + /* GPIO-J on the Dragonboard Dual-Leopard OV5640 board */ + powerdown-gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>; + /* GPIO-I on the Dragonboard Dual-Leopard OV5640 board */ + reset-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&stmipi_0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&stmipi { + status = "okay"; +}; + +&stmipi_0 { + data-lanes = <1 2>; + remote-endpoint = <&ov5640_0>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso new file mode 100644 index 000000000000..acfd25c5bbcd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + cs-gpios = <&gpioi 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso new file mode 100644 index 000000000000..aa79f95906f8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&sdmmc3 { + broken-cd; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi new file mode 100644 index 000000000000..be9eb1e11ecd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + lvds-encoder { + compatible = "onnn,fin3385", "lvds-encoder"; + pclk-sample = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_bridge_in: endpoint { + remote-endpoint = <<dc_dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&display_bl { + pwms = <&pwm2 3 5000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + ili251x@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <16384>; + touchscreen-size-y = <9600>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&lvds_bridge_in>; +}; + +&panel { + compatible = "chefree,ch101olhlwh-002"; +}; + +&panel_in { + remote-endpoint = <&lvds_bridge_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi new file mode 100644 index 000000000000..41229ec680cc --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +#include +#include +#include +#include + +&{/} { + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_panel_bl>; + status = "okay"; + }; + + panel: panel { + backlight = <&display_bl>; + power-supply = <®_panel_bl>; + + port { + panel_in: endpoint { + }; + }; + }; + + reg_panel_bl: regulator-panel-bl { + compatible = "regulator-fixed"; + regulator-name = "panel_backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_panel_supply>; + }; + + reg_panel_supply: regulator-panel-supply { + compatible = "regulator-fixed"; + regulator-name = "panel_supply"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; +}; + +&timers2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pwm2: pwm { + #pwm-cells = <3>; + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@1 { + reg = <1>; + status = "okay"; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + ltdc_dpi_out: endpoint { + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso new file mode 100644 index 000000000000..161e401f5e21 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&fmc { + #address-cells = <2>; + #size-cells = <1>; + + sram@3,0 { + compatible = "mtd-ram"; + reg = <3 0x0 0x80000>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <6>; + st,fmc2-ebi-cs-address-hold-ns = <6>; + st,fmc2-ebi-cs-data-setup-ns = <127>; + st,fmc2-ebi-cs-bus-turnaround-ns = <9>; + st,fmc2-ebi-cs-data-hold-ns = <9>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso new file mode 100644 index 000000000000..1de244545054 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "dataimage,scf0700c48ggu18"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso new file mode 100644 index 000000000000..6ef9bcf527ad --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" + +&{/} { + gpio-keys-polled { + /* BUTTON1 GPIO-B conflicts with touchscreen reset */ + button-1 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; + + led { + /* LED7 GPIO-H conflicts with touchscreen IRQ */ + led-2 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso new file mode 100644 index 000000000000..ce291736abbb --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "okay"; + cs-gpios = <&gpioz 3 0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso new file mode 100644 index 000000000000..7e040b2d8f24 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +/* SPI2 is not connected on STM32MP1 DHCOM SoM */ diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso new file mode 100644 index 000000000000..a5cef9ba7dd2 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + gpio-keys { + /* + * The EXTi IRQ line 6 is shared with touchscreen IRQ, + * so operate button-1 as polled GPIO key. + */ + button-1 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; + + gpio-keys-polled { + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + }; + }; + + led { + /* LED5 GPIO-E conflicts with touchscreen IRQ */ + led-0 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; +}; + +&display_bl { + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */ + interrupt-parent = <&gpioc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "edt,etm0700g0edh6"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso new file mode 100644 index 000000000000..ee8a2d1a7b87 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: touchscreen@38 { + }; + + attiny: regulator@45 { + }; +}; + +#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi" + +<dc { + status = "okay"; + port { + ltdc_ep_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso new file mode 100644 index 000000000000..41e473986189 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 5c77202ee196..0075d9391181 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -13,15 +13,6 @@ clk_ext_audio_codec: clock-codec { clock-frequency = <24000000>; }; - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - power-supply = <®_panel_bl>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; poll-interval = <20>; @@ -75,7 +66,6 @@ led-0 { label = "green:led5"; gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; default-state = "off"; - status = "disabled"; }; led-1 { @@ -97,33 +87,6 @@ led-3 { }; }; - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - power-supply = <®_panel_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_panel_bl: regulator-panel-bl { - compatible = "regulator-fixed"; - regulator-name = "panel_backlight"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_panel_supply>; - }; - - reg_panel_supply: regulator-panel-supply { - compatible = "regulator-fixed"; - regulator-name = "panel_supply"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - sound { compatible = "audio-graph-card"; widgets = "Headphone", "Headphone Jack", @@ -188,26 +151,6 @@ sgtl5000_rx_endpoint: endpoint@1 { }; }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpioc>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_sleep_pins_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; &sai2 { @@ -259,21 +202,6 @@ sai2b_endpoint: endpoint { }; }; -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso new file mode 100644 index 000000000000..c462c6a08833 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Andreas Geisreiter + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 10000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "multi-inno,mi0700s4t-6"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso new file mode 100644 index 000000000000..06338b7f7b67 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 10000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "team-source-display,tst043015cmhx"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso new file mode 100644 index 000000000000..bf5c1f6eece0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index aceeff6c38ba..85d93ddfa12a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -258,15 +258,9 @@ &i2c2 { /* X6 I2C2 */ &i2c4 { stmipi: stmipi@14 { compatible = "st,st-mipid02"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mco1_pins_a>; - pinctrl-1 = <&mco1_sleep_pins_a>; reg = <0x14>; clocks = <&rcc CK_MCO1>; clock-names = "xclk"; - assigned-clocks = <&rcc CK_MCO1>; - assigned-clock-parents = <&rcc CK_HSE>; - assigned-clock-rates = <24000000>; VDDE-supply = <&v1v8>; VDDIN-supply = <&v1v8>; reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi new file mode 100644 index 000000000000..518c269a1dba --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +#include + +&{/} { + panel { + compatible = "powertip,ph800480t013-idf02"; + backlight = <&attiny>; + power-supply = <&attiny>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&attiny { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x45>; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + phy-dsi-supply = <®18>; + status = "okay"; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + reset-gpios = <&attiny 0 GPIO_ACTIVE_HIGH>; + vddc-supply = <&attiny>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&touchscreen { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + reset-gpios = <&attiny 1 GPIO_ACTIVE_LOW>; + /* + * Disabled, since the IRQ line is not on + * the FPC cable, so we cannot get touch + * IRQs unless its connected otherwise. In + * that case, add entry like this one and + * enable below. + * + * interrupt-parent = <&gpiog>; + * interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 7ed2b01958fe..599ea07bdb19 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -155,6 +155,46 @@ &crc1 { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dts { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi new file mode 100644 index 000000000000..f7e7aa9b916a --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; +}; + +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_d>; + pinctrl-1 = <&dcmi_sleep_pins_d>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_f>; + pinctrl-1 = <<dc_sleep_pins_f>; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_d>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_d>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + st,sync = <&sai2b 2>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + vmmc-supply = <&v3v3>; + st,neg-edge; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&timers5 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm5: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_c>; + pinctrl-1 = <&pwm5_sleep_pins_c>; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_f>; + pinctrl-1 = <&uart4_sleep_pins_f>; + pinctrl-2 = <&uart4_idle_pins_f>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + status = "okay"; +}; + +&usbh_ohci { + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi similarity index 53% rename from arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi index 370b2afbf15b..126446c4198f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -1,23 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) 2022-2023 Steffen Trumtrar * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD . + * Author: Dom VOVARD + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Christophe Parant */ #include #include -#include -#include -#include -#include #include #include #include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" / { - model = "PHYTEC phyCORE-STM32MP15 SOM"; - compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; aliases { ethernet0 = ðernet0; @@ -25,24 +22,13 @@ aliases { rtc1 = &rtc; }; - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "Home"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-enter { - label = "Enter"; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; }; reserved-memory { @@ -50,18 +36,6 @@ reserved-memory { #size-cells = <1>; ranges; - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - mcuram2: mcuram2@10000000 { compatible = "shared-dma-pool"; reg = <0x10000000 0x40000>; @@ -85,21 +59,23 @@ vdev0buffer: vdev0buffer@10042000 { reg = <0x10042000 0x4000>; no-map; }; - }; - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-PHYCORE"; - routing = - "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ - "Capture", "MCLK"; - dais = <&sai2b_port>, - <&sai2a_port>; + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; }; regulator_vin: regulator { compatible = "regulator-fixed"; - regulator-name = "vin"; + regulator-name = "VIN"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; @@ -126,101 +102,28 @@ phy0: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpiog>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; - enet-phy-lane-no-swap; ti,clk-output-sel = ; }; }; }; -&i2c1 { +&fmc { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-1 = <&i2c1_sleep_pins_b>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "disabled"; - codec@18 { - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - #sound-dai-cells = <0>; - - ai3x-micbias-vg = <2>; - - AVDD-supply = <&v3v3>; - IOVDD-supply = <&v3v3>; - DRVDD-supply = <&v3v3>; - DVDD-supply = <&v1v8_audio>; - - clocks = <&sai2b>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tlv320_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - - tlv320_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - }; - }; - - touch@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioi>; - vio-supply = <&v3v3>; - vcc-supply = <&v3v3>; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - - touchscreen { - compatible = "st,stmpe-ts"; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-0 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-1 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-2 { - color = ; - function = LED_FUNCTION_HEARTBEAT; - type = ; - linux,default-trigger = "heartbeat"; + nand-controller@4,0 { + nand0: nand@0 { + reg = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; }; }; }; @@ -257,7 +160,7 @@ regulators { pwr_sw2-supply = <&bst_out>; vddcore: buck1 { - regulator-name = "vddcore"; + regulator-name = "VDD_CORE"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -265,7 +168,7 @@ vddcore: buck1 { }; vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; + regulator-name = "VDD_DDR"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -273,7 +176,7 @@ vdd_ddr: buck2 { }; vdd: buck3 { - regulator-name = "vdd"; + regulator-name = "VDD"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -282,7 +185,7 @@ vdd: buck3 { }; v3v3: buck4 { - regulator-name = "v3v3"; + regulator-name = "VDD_BUCK4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -290,7 +193,7 @@ v3v3: buck4 { }; v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; + regulator-name = "VDD_LDO1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -299,7 +202,7 @@ v1v8_audio: ldo1 { }; vdd_eth_2v5: ldo2 { - regulator-name = "dd_eth_2v5"; + regulator-name = "VDD_ETH_2V5"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; @@ -308,7 +211,7 @@ vdd_eth_2v5: ldo2 { }; vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; + regulator-name = "VTT_DDR"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <750000>; regulator-always-on; @@ -316,12 +219,12 @@ vtt_ddr: ldo3 { }; vdd_usb: ldo4 { - regulator-name = "vdd_usb"; + regulator-name = "VDD_USB"; interrupts = ; }; vdda: ldo5 { - regulator-name = "vdda"; + regulator-name = "VDDA"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; @@ -329,7 +232,7 @@ vdda: ldo5 { }; vdd_eth_1v0: ldo6 { - regulator-name = "vdd_eth_1v0"; + regulator-name = "VDD_ETH_1V0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -338,23 +241,23 @@ vdd_eth_1v0: ldo6 { }; vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; + regulator-name = "VDD_REFDDR"; regulator-always-on; }; bst_out: boost { - regulator-name = "bst_out"; + regulator-name = "BST_OUT"; interrupts = ; }; vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; + regulator-name = "VBUS_OTG"; interrupts = ; regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; + regulator-name = "VBUS_SW"; interrupts = ; regulator-active-discharge = <1>; }; @@ -375,14 +278,15 @@ watchdog { }; i2c4_eeprom: eeprom@50 { - compatible = "microchip,24c32", - "atmel,24c32"; + compatible = "atmel,24c32"; reg = <0x50>; + status = "disabled"; }; i2c4_rtc: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + status = "disabled"; }; }; @@ -395,13 +299,6 @@ &iwdg2 { status = "okay"; }; -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; - &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; @@ -419,18 +316,22 @@ &pwr_regulators { &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - status = "okay"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, + <0x70000000 0x1000000>; + status = "disabled"; flash0: flash@0 { - compatible = "winbond,w25q128", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; m25p,fast-read; - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -442,56 +343,7 @@ &rtc { status = "okay"; }; -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; - pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; - status = "okay"; -}; - -&sai2a { - dma-names = "rx"; - st,sync = <&sai2b 2>; - clocks = <&rcc SAI2_K>, <&sai2b>; - clock-names = "sai_ck", "MCLK"; - #clock-cells = <0>; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&tlv320_rx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sai2b { - dma-names = "tx"; - #clock-cells = <0>; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&tlv320_tx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; - cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; +&dts { status = "okay"; }; @@ -503,71 +355,10 @@ &sdmmc2 { non-removable; no-sd; no-sdio; - st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&v3v3>; mmc-ddr-3_3v; -}; - -&spi1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_a>; - pinctrl-1 = <&spi1_sleep_pins_a>; - cs-gpios = <&gpioz 3 0>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - pinctrl-3 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usart1 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; - pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; - pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_a>; - pinctrl-1 = <&usart3_sleep_pins_a>; - pinctrl-2 = <&usart3_idle_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - status = "okay"; -}; - -&usbh_ohci { - status = "okay"; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; + st,neg-edge; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi index cd078a16065e..4bfd58b26b51 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -112,6 +112,22 @@ usart2: serial@400e0000 { }; }; + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp21-syscfg", "syscon"; reg = <0x44230000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..a1285abc80ca 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + &usart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index b5d81d1ee153..9e1d240888ff 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -45,6 +45,12 @@ clk_dsi_txbyte: clock-0 { clock-frequency = <0>; }; + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + clk_rcbsec: clk-64000000 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -354,7 +360,7 @@ i2c1: i2c@40120000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C1>; resets = <&rcc I2C1_R>; dmas = <&hpdma 27 0x20 0x3012>, @@ -363,6 +369,7 @@ i2c1: i2c@40120000 { access-controllers = <&rifsc 41>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -372,7 +379,7 @@ i2c2: i2c@40130000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C2>; resets = <&rcc I2C2_R>; dmas = <&hpdma 30 0x20 0x3012>, @@ -381,6 +388,7 @@ i2c2: i2c@40130000 { access-controllers = <&rifsc 42>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -390,7 +398,7 @@ i2c7: i2c@40180000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C7>; resets = <&rcc I2C7_R>; dmas = <&hpdma 45 0x20 0x3012>, @@ -399,6 +407,7 @@ i2c7: i2c@40180000 { access-controllers = <&rifsc 47>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -668,7 +677,7 @@ i2c8: i2c@46040000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti2 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C8>; resets = <&rcc I2C8_R>; dmas = <&hpdma 168 0x20 0x3012>, @@ -677,6 +686,7 @@ i2c8: i2c@46040000 { access-controllers = <&rifsc 48>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -970,6 +980,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible = "st,stm32mp23-syscfg", "syscon"; reg = <0x44230000 0x10000>; + #clock-cells = <0>; }; pinctrl: pinctrl@44240000 { @@ -1193,6 +1204,18 @@ exti2: interrupt-controller@46230000 { <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp251-ltdc"; + reg = <0x48010000 0x400>; + interrupts = , + ; + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names = "lcd", "bus"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + intc: interrupt-controller@4ac10000 { compatible = "arm,gic-400"; reg = <0x4ac10000 0x1000>, diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi index 2719c088dd59..7a87c344a4fe 100644 --- a/arch/arm64/boot/dts/st/stm32mp235.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi @@ -5,7 +5,25 @@ */ #include "stm32mp233.dtsi" +<dc { + compatible = "st,stm32mp255-ltdc"; + clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + clock-names = "lcd", "bus", "ref", "lvds"; +}; + &rifsc { + lvds: lvds@48060000 { + compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + reg = <0x48060000 0x2000>; + #clock-cells = <0>; + clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names = "pclk", "ref"; + resets = <&rcc LVDS_R>; + access-controllers = <&rifsc 84>; + power-domains = <&cluster_pd>; + status = "disabled"; + }; + vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 5ecc5ef61590..dd4efbe5a46e 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -77,6 +77,42 @@ u-boot { }; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -117,11 +153,105 @@ phy1_eth1: ethernet-phy@1 { }; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; scmi_vdd_sdcard: regulator@23 { reg = ; regulator-name = "vdd_sdcard"; diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index c34cd33cd855..456ece7f8ebc 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,7 @@ #include &pinctrl { + /omit-if-no-ref/ eth1_mdio_pins_a: eth1-mdio-0 { pins1 { pinmux = ; /* ETH_MDC */ @@ -21,6 +22,7 @@ pins2 { }; }; + /omit-if-no-ref/ eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { pins1 { pinmux = , /* ETH_MDC */ @@ -28,6 +30,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -62,6 +65,7 @@ pins4 { }; }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -80,6 +84,7 @@ pins { }; }; + /omit-if-no-ref/ eth1_rgmii_pins_b: eth1-rgmii-1 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -114,6 +119,7 @@ pins4 { }; }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -134,6 +140,7 @@ pins { }; }; + /omit-if-no-ref/ eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -175,6 +182,7 @@ pins5 { }; }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -195,6 +203,7 @@ pins { }; }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ @@ -205,6 +214,7 @@ pins { }; }; + /omit-if-no-ref/ i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = , /* I2C2_SCL */ @@ -212,6 +222,26 @@ pins { }; }; + /omit-if-no-ref/ + i2c2_pins_b: i2c2-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c2_sleep_pins_b: i2c2-sleep-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { pinmux = ; /* OSPI1_CLK */ @@ -221,12 +251,14 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 { pins { pinmux = ; /* OSPI1_CLK */ }; }; + /omit-if-no-ref/ ospi_port1_cs0_pins_a: ospi-port1-cs0-0 { pins { pinmux = ; /* OSPI_NCS0 */ @@ -236,12 +268,14 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 { pins { pinmux = ; /* OSPI_NCS0 */ }; }; + /omit-if-no-ref/ ospi_port1_io03_pins_a: ospi-port1-io03-0 { pins { pinmux = , /* OSPI_IO0 */ @@ -254,6 +288,7 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 { pins { pinmux = , /* OSPI_IO0 */ @@ -263,6 +298,7 @@ pins { }; }; + /omit-if-no-ref/ pcie_pins_a: pcie-0 { pins { pinmux = ; @@ -270,6 +306,7 @@ pins { }; }; + /omit-if-no-ref/ pcie_init_pins_a: pcie-init-0 { pins { pinmux = ; @@ -277,12 +314,14 @@ pins { }; }; + /omit-if-no-ref/ pcie_sleep_pins_a: pcie-sleep-0 { pins { pinmux = ; }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH2 */ @@ -292,12 +331,14 @@ pins { }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = ; /* TIM3_CH2 */ }; }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = , /* TIM8_CH1 */ @@ -308,6 +349,7 @@ pins { }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = , /* TIM8_CH1 */ @@ -315,6 +357,7 @@ pins { }; }; + /omit-if-no-ref/ pwm12_pins_a: pwm12-0 { pins { pinmux = ; /* TIM12_CH2 */ @@ -324,12 +367,14 @@ pins { }; }; + /omit-if-no-ref/ pwm12_sleep_pins_a: pwm12-sleep-0 { pins { pinmux = ; /* TIM12_CH2 */ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -349,6 +394,7 @@ pins2 { }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -373,6 +419,7 @@ pins3 { }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -384,6 +431,7 @@ pins { }; }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -398,6 +446,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi3_sleep_pins_a: spi3-sleep-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -406,6 +455,7 @@ pins1 { }; }; + /omit-if-no-ref/ tim10_counter_pins_a: tim10-counter-0 { pins { pinmux = ; /* TIM10_CH1 */ @@ -413,6 +463,7 @@ pins { }; }; + /omit-if-no-ref/ tim10_counter_sleep_pins_a: tim10-counter-sleep-0 { pins { pinmux = ; /* TIM10_CH1 */ @@ -420,6 +471,7 @@ pins { }; }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -433,6 +485,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_idle_pins_a: usart2-idle-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -443,6 +496,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = , /* USART2_TX */ @@ -450,6 +504,7 @@ pins { }; }; + /omit-if-no-ref/ usart6_pins_a: usart6-0 { pins1 { pinmux = , /* USART6_TX */ @@ -465,6 +520,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart6_idle_pins_a: usart6-idle-0 { pins1 { pinmux = , /* USART6_TX */ @@ -482,6 +538,7 @@ pins3 { }; }; + /omit-if-no-ref/ usart6_sleep_pins_a: usart6-sleep-0 { pins { pinmux = , /* USART6_TX */ @@ -493,6 +550,7 @@ pins { }; &pinctrl_z { + /omit-if-no-ref/ i2c8_pins_a: i2c8-0 { pins { pinmux = , /* I2C8_SCL */ @@ -503,15 +561,15 @@ pins { }; }; + /omit-if-no-ref/ i2c8_sleep_pins_a: i2c8-sleep-0 { pins { pinmux = , /* I2C8_SCL */ ; /* I2C8_SDA */ }; }; -}; -&pinctrl_z { + /omit-if-no-ref/ spi8_pins_a: spi8-0 { pins1 { pinmux = , /* SPI8_SCK */ @@ -526,6 +584,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi8_sleep_pins_a: spi8-sleep-0 { pins1 { pinmux = , /* SPI8_SCK */ diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8b925ed0d881..673fbc5632e6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -773,7 +773,7 @@ i2c1: i2c@40120000 { compatible = "st,stm32mp25-i2c"; reg = <0x40120000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C1>; resets = <&rcc I2C1_R>; #address-cells = <1>; @@ -784,6 +784,7 @@ i2c1: i2c@40120000 { access-controllers = <&rifsc 41>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -791,7 +792,7 @@ i2c2: i2c@40130000 { compatible = "st,stm32mp25-i2c"; reg = <0x40130000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C2>; resets = <&rcc I2C2_R>; #address-cells = <1>; @@ -802,6 +803,7 @@ i2c2: i2c@40130000 { access-controllers = <&rifsc 42>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -809,7 +811,7 @@ i2c3: i2c@40140000 { compatible = "st,stm32mp25-i2c"; reg = <0x40140000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C3>; resets = <&rcc I2C3_R>; #address-cells = <1>; @@ -820,6 +822,7 @@ i2c3: i2c@40140000 { access-controllers = <&rifsc 43>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -827,7 +830,7 @@ i2c4: i2c@40150000 { compatible = "st,stm32mp25-i2c"; reg = <0x40150000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C4>; resets = <&rcc I2C4_R>; #address-cells = <1>; @@ -838,6 +841,7 @@ i2c4: i2c@40150000 { access-controllers = <&rifsc 44>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -845,7 +849,7 @@ i2c5: i2c@40160000 { compatible = "st,stm32mp25-i2c"; reg = <0x40160000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C5>; resets = <&rcc I2C5_R>; #address-cells = <1>; @@ -856,6 +860,7 @@ i2c5: i2c@40160000 { access-controllers = <&rifsc 45>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -863,7 +868,7 @@ i2c6: i2c@40170000 { compatible = "st,stm32mp25-i2c"; reg = <0x40170000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C6>; resets = <&rcc I2C6_R>; #address-cells = <1>; @@ -874,6 +879,7 @@ i2c6: i2c@40170000 { access-controllers = <&rifsc 46>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -881,7 +887,7 @@ i2c7: i2c@40180000 { compatible = "st,stm32mp25-i2c"; reg = <0x40180000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C7>; resets = <&rcc I2C7_R>; #address-cells = <1>; @@ -892,6 +898,7 @@ i2c7: i2c@40180000 { access-controllers = <&rifsc 47>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -1473,7 +1480,7 @@ i2c8: i2c@46040000 { compatible = "st,stm32mp25-i2c"; reg = <0x46040000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti2 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C8>; resets = <&rcc I2C8_R>; #address-cells = <1>; @@ -1484,6 +1491,7 @@ i2c8: i2c@46040000 { access-controllers = <&rifsc 48>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index 4135e7c0d9a3..8daf3dfd5133 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -84,6 +84,42 @@ u-boot { }; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -124,11 +160,105 @@ phy1_eth1: ethernet-phy@1 { }; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; scmi_vdd_sdcard: regulator@23 { reg = ; regulator-name = "vdd_sdcard"; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 852a73b0c516..14e033f365e3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -261,6 +261,9 @@ &i2c2 { i2c-scl-falling-time-ns = <13>; clock-frequency = <400000>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; imx335: camera@1a { compatible = "sony,imx335"; @@ -299,6 +302,9 @@ &i2c8 { i2c-scl-falling-time-ns = <7>; clock-frequency = <400000>; status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; }; &ommanager { diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b67d5b1fc45b..45b7803a54c5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -482,6 +482,7 @@ CONFIG_TOUCHSCREEN_APPLE_Z2=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_GOODIX=m CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m +CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m @@ -977,6 +978,8 @@ CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m +CONFIG_DRM_STM=m +CONFIG_DRM_STM_LVDS=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m @@ -1053,6 +1056,7 @@ CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_APPLE_DWI=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=m CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set