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net/mlx5: Create a new profile for SFs
Create a new profile for SFs in order to disable the command cache. Each function command cache consumes ~500KB of memory, when using a large number of SFs this savings is notable on memory constarined systems. Use a new profile to provide for future differences between SFs and PFs. The mr_cache not used for non-PF functions, so it is excluded from the new profile. Signed-off-by: Parav Pandit <parav@mellanox.com> Reviewed-by: Bodong Wang <bodong@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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@ -1802,7 +1802,7 @@ static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
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if (in_size <= 16)
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goto cache_miss;
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for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
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for (i = 0; i < dev->profile.num_cmd_caches; i++) {
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ch = &cmd->cache[i];
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if (in_size > ch->max_inbox_size)
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continue;
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@ -2097,7 +2097,7 @@ static void destroy_msg_cache(struct mlx5_core_dev *dev)
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struct mlx5_cmd_msg *n;
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int i;
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for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
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for (i = 0; i < dev->profile.num_cmd_caches; i++) {
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ch = &dev->cmd.cache[i];
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list_for_each_entry_safe(msg, n, &ch->head, list) {
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list_del(&msg->list);
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@ -2127,7 +2127,7 @@ static void create_msg_cache(struct mlx5_core_dev *dev)
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int k;
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/* Initialize and fill the caches with initial entries */
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for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
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for (k = 0; k < dev->profile.num_cmd_caches; k++) {
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ch = &cmd->cache[k];
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spin_lock_init(&ch->lock);
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INIT_LIST_HEAD(&ch->head);
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@ -100,15 +100,19 @@ enum {
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static struct mlx5_profile profile[] = {
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[0] = {
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.mask = 0,
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.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
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},
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[1] = {
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.mask = MLX5_PROF_MASK_QP_SIZE,
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.log_max_qp = 12,
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.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
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},
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[2] = {
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.mask = MLX5_PROF_MASK_QP_SIZE |
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MLX5_PROF_MASK_MR_CACHE,
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.log_max_qp = LOG_MAX_SUPPORTED_QPS,
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.num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
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.mr_cache[0] = {
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.size = 500,
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.limit = 250
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@ -174,6 +178,11 @@ static struct mlx5_profile profile[] = {
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.limit = 4
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},
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},
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[3] = {
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.mask = MLX5_PROF_MASK_QP_SIZE,
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.log_max_qp = LOG_MAX_SUPPORTED_QPS,
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.num_cmd_caches = 0,
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},
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};
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static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
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@ -142,6 +142,7 @@ enum mlx5_semaphore_space_address {
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};
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#define MLX5_DEFAULT_PROF 2
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#define MLX5_SF_PROF 3
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static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed,
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size_t item_size, size_t num_items,
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@ -28,7 +28,7 @@ static int mlx5_sf_dev_probe(struct auxiliary_device *adev, const struct auxilia
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mdev->priv.adev_idx = adev->id;
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sf_dev->mdev = mdev;
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err = mlx5_mdev_init(mdev, MLX5_DEFAULT_PROF);
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err = mlx5_mdev_init(mdev, MLX5_SF_PROF);
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if (err) {
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mlx5_core_warn(mdev, "mlx5_mdev_init on err=%d\n", err);
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goto mdev_err;
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@ -751,6 +751,7 @@ enum {
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struct mlx5_profile {
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u64 mask;
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u8 log_max_qp;
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u8 num_cmd_caches;
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struct {
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int size;
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int limit;
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