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ARM: dts: ti: Drop unused .dtsi
These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251212203226.458694-6-robh@kernel.org Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Rob Herring (Arm)
Kevin Hilman
parent
3d43205d0e
commit
9da91ec4a6
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@ -1,14 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
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*/
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#include "omap36xx.dtsi"
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&iva {
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status = "disabled";
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};
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&sgx_module {
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status = "disabled";
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};
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@ -1,10 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
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*/
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#include "omap36xx.dtsi"
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&iva {
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status = "disabled";
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};
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@ -1,237 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP3430 ES1 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*/
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&cm_clocks {
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gfx_l3_ck: gfx_l3_ck@b10 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&l3_ick>;
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reg = <0x0b10>;
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ti,bit-shift = <0>;
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};
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gfx_l3_fck: gfx_l3_fck@b40 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l3_ick>;
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ti,max-div = <7>;
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reg = <0x0b40>;
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ti,index-starts-at-one;
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};
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gfx_l3_ick: gfx_l3_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&gfx_l3_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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gfx_cg1_ck: gfx_cg1_ck@b00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <1>;
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};
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gfx_cg2_ck: gfx_cg2_ck@b00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&gfx_l3_fck>;
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reg = <0x0b00>;
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ti,bit-shift = <2>;
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};
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clock@a00 {
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compatible = "ti,clksel";
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reg = <0xa00>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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d2d_26m_fck: clock-d2d-26m-fck@3 {
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reg = <3>;
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "d2d_26m_fck";
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clocks = <&sys_ck>;
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};
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fshostusb_fck: clock-fshostusb-fck@5 {
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reg = <5>;
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "fshostusb_fck";
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clocks = <&core_48m_fck>;
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};
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ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
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reg = <0>;
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clock-output-names = "ssi_ssr_gate_fck_3430es1";
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clocks = <&corex2_fck>;
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};
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};
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clock@a40 {
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compatible = "ti,clksel";
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reg = <0xa40>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
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reg = <8>;
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "ssi_ssr_div_fck_3430es1";
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clocks = <&corex2_fck>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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usb_l4_div_ick: clock-usb-l4-div-ick@4 {
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reg = <4>;
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "usb_l4_div_ick";
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clocks = <&l4_ick>;
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ti,max-div = <1>;
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ti,index-starts-at-one;
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};
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};
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ssi_ssr_fck: ssi_ssr_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
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};
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ssi_sst_fck: ssi_sst_fck_3430es1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&ssi_ssr_fck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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clock@a10 {
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compatible = "ti,clksel";
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reg = <0xa10>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
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reg = <4>;
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clock-output-names = "hsotgusb_ick_3430es1";
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clocks = <&core_l3_ick>;
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};
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fac_ick: clock-fac-ick@8 {
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reg = <8>;
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clock-output-names = "fac_ick";
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clocks = <&core_l4_ick>;
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};
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ssi_ick: clock-ssi-ick-3430es1@0 {
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reg = <0>;
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clock-output-names = "ssi_ick_3430es1";
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clocks = <&ssi_l4_ick>;
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};
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usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
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reg = <5>;
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clock-output-names = "usb_l4_gate_ick";
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clocks = <&l4_ick>;
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};
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};
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ssi_l4_ick: ssi_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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usb_l4_ick: usb_l4_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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clock@e00 {
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compatible = "ti,clksel";
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reg = <0xe00>;
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
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reg = <0>;
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clock-output-names = "dss1_alwon_fck_3430es1";
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clocks = <&dpll4_m4x2_ck>;
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ti,set-rate-parent;
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};
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};
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dss_ick: dss_ick_3430es1@e10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x0e10>;
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ti,bit-shift = <0>;
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};
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};
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&cm_clockdomains {
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
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};
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gfx_3430es1_clkdm: gfx_3430es1_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
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<&dss1_alwon_fck>, <&dss_ick>;
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};
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d2d_clkdm: d2d_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&d2d_26m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
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};
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};
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