From 9da65c6c17434b862d94189068422040278869cd Mon Sep 17 00:00:00 2001 From: David Wu Date: Thu, 8 Mar 2018 16:07:48 +0800 Subject: [PATCH] arm64: dts: rockchip: Add pwm 4 channels for rk3308 Change-Id: Iba2e94d037c6d3e2fa5b4f1217d4e32ff7c35bca Signed-off-by: David Wu --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 8ad338e2a1e0..43b29faebd7f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -168,6 +168,50 @@ uart1: serial@ff0b0000 { status = "disabled"; }; + pwm0: pwm@ff180000 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ff180010 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ff180020 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ff180030 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + i2s0: i2s@ff300000 { compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff300000 0x0 0x10000>;