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arm64: dts: rockchip: rk3588: Fix pcie module clock

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PCIe need pipe clock for interface with phy;

Note that pcie controller also need its clock(has been set critical)
ACLK_PHP_GIC_ITS, and ACLK_PCIE_BRIDGE(has been set as parent).

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I98b2c001e8d0568af482cef8702a73a6cbd661f6
This commit is contained in:
Kever Yang 2021-11-26 11:35:54 +08:00 committed by Tao Huang
parent 9e1ddefd50
commit 9d98b3fedd
2 changed files with 15 additions and 10 deletions
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15
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@ -466,9 +466,10 @@ pcie3x4: pcie@fe150000 {
bus-range = <0x00 0x0f>;
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
<&cru CLK_PCIE_AUX0>;
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
@ -518,9 +519,10 @@ pcie3x2: pcie@fe160000 {
bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
<&cru CLK_PCIE_AUX1>;
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@ -570,9 +572,10 @@ pcie2x1l0: pcie@fe170000 {
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
<&cru CLK_PCIE_AUX2>;
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,

10
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@ -3028,9 +3028,10 @@ pcie2x1l1: pcie@fe180000 {
bus-range = <0x30 0x3f>;
clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
<&cru CLK_PCIE_AUX3>;
<&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
@ -3080,9 +3081,10 @@ pcie2x1l2: pcie@fe190000 {
bus-range = <0x40 0x4f>;
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
<&cru CLK_PCIE_AUX4>;
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,