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wifi: rtw89: 8922d: add quota for RTL8922DE variant
The existing quota set is for RTL8922DE-VS, so rename the existing tables. Add new quota set for RTL8922DE, containing more memory to yield better performance, so rearrange quota accordingly. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260515014433.16168-14-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
parent
77be46f281
commit
9d69ffa4f8
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@ -1748,6 +1748,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,},
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/* 8852C PCIE SCC */
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.wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
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.wde_size22_v1 = {RTW89_WDE_PG_128, 384, 0, 0,},
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.wde_size23 = {RTW89_WDE_PG_64, 1022, 2,},
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/* 8852B USB2.0/USB3.0 SCC turbo */
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.wde_size30 = {RTW89_WDE_PG_64, 220, 36,},
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@ -1781,6 +1782,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,},
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/* 8851B USB2.0 SCC turbo */
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.ple_size27 = {RTW89_PLE_PG_128, 1396, 12,},
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.ple_size29_v1 = {RTW89_PLE_PG_128, 1895, 182, 49152,},
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/* 8852B USB3.0 SCC turbo */
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.ple_size31 = {RTW89_PLE_PG_128, 1392, 16,},
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/* 8852C USB2.0 */
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@ -1811,6 +1813,7 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.wde_qt18 = {3228, 60, 0, 40,},
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.wde_qt19_v1 = {613, 6, 0, 20,},
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.wde_qt23 = {958, 48, 0, 16,},
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.wde_qt23_v1 = {371, 3, 0, 10,},
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/* 8852B USB2.0/USB3.0 SCC turbo */
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.wde_qt30 = {210, 2, 0, 8,},
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/* 8852C USB2.0 */
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@ -1868,6 +1871,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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/* 8851B USB2.0 SCC turbo */
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.ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,},
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.ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,},
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.ple_qt64_v2 = {91, 91, 32, 16, 19, 13, 93, 93, 44, 34, 1, 4, 0, 0,},
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.ple_qt65_v2 = {645, 645, 32, 1380, 1383, 1377, 1457, 1457, 1408, 1398, 1, 1368,},
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/* USB2.0 52C */
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.ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,},
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/* USB2.0 52C */
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@ -1888,10 +1893,13 @@ const struct rtw89_mac_size_set rtw89_mac_size = {
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.rsvd0_size3 = {57344, 0,},
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.rsvd0_size5 = {32768, 0,},
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.rsvd0_size6 = {40960, 0,},
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.rsvd0_size17 = {49152, 0,},
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.rsvd1_size0 = {587776, 2048,},
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.rsvd1_size2 = {391168, 2048,},
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.rsvd1_size3 = {315008, 78208,},
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.dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0, 0,},
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.dle_input20 = {128, 128, 11454, 2048, 0, 2048, 1024, 24, 24,},
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.dle_input28 = {128, 128, 11454, 2048, 0, 2048, 2048, 24, 24,},
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};
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EXPORT_SYMBOL(rtw89_mac_size);
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@ -946,6 +946,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size wde_size18;
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const struct rtw89_dle_size wde_size18_v1;
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const struct rtw89_dle_size wde_size19;
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const struct rtw89_dle_size wde_size22_v1;
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const struct rtw89_dle_size wde_size23;
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const struct rtw89_dle_size wde_size30;
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const struct rtw89_dle_size wde_size31;
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@ -966,6 +967,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_size ple_size20_v1;
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const struct rtw89_dle_size ple_size22_v1;
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const struct rtw89_dle_size ple_size27;
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const struct rtw89_dle_size ple_size29_v1;
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const struct rtw89_dle_size ple_size31;
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const struct rtw89_dle_size ple_size34;
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const struct rtw89_wde_quota wde_qt0;
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@ -984,6 +986,7 @@ struct rtw89_mac_size_set {
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const struct rtw89_wde_quota wde_qt18;
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const struct rtw89_wde_quota wde_qt19_v1;
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const struct rtw89_wde_quota wde_qt23;
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const struct rtw89_wde_quota wde_qt23_v1;
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const struct rtw89_wde_quota wde_qt30;
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const struct rtw89_wde_quota wde_qt31;
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const struct rtw89_ple_quota ple_qt0;
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@ -1020,6 +1023,8 @@ struct rtw89_mac_size_set {
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const struct rtw89_ple_quota ple_qt59;
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const struct rtw89_ple_quota ple_qt61;
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const struct rtw89_ple_quota ple_qt62;
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const struct rtw89_ple_quota ple_qt64_v2;
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const struct rtw89_ple_quota ple_qt65_v2;
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const struct rtw89_ple_quota ple_qt78;
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const struct rtw89_ple_quota ple_qt79;
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const struct rtw89_ple_quota ple_qt_52a_wow;
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@ -1035,10 +1040,13 @@ struct rtw89_mac_size_set {
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const struct rtw89_dle_rsvd_size rsvd0_size3;
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const struct rtw89_dle_rsvd_size rsvd0_size5;
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const struct rtw89_dle_rsvd_size rsvd0_size6;
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const struct rtw89_dle_rsvd_size rsvd0_size17;
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const struct rtw89_dle_rsvd_size rsvd1_size0;
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const struct rtw89_dle_rsvd_size rsvd1_size2;
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const struct rtw89_dle_rsvd_size rsvd1_size3;
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const struct rtw89_dle_input dle_input3;
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const struct rtw89_dle_input dle_input20;
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const struct rtw89_dle_input dle_input28;
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};
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extern const struct rtw89_mac_size_set rtw89_mac_size;
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@ -25,6 +25,62 @@
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RTW89_GEN_MODULE_FWNAME(RTW8922DS_FW_BASENAME, RTW8922DS_FW_FORMAT_MAX)
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static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
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{2, 732, 0}, /* ACH 0 */
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{0, 730, 0}, /* ACH 1 */
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{2, 732, 0}, /* ACH 2 */
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{0, 730, 0}, /* ACH 3 */
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{2, 732, 0}, /* ACH 4 */
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{0, 730, 0}, /* ACH 5 */
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{2, 732, 0}, /* ACH 6 */
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{0, 730, 0}, /* ACH 7 */
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{2, 732, 0}, /* B0MGQ */
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{0, 730, 0}, /* B0HIQ */
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{2, 732, 0}, /* B1MGQ */
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{0, 730, 0}, /* B1HIQ */
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{0, 0, 0}, /* GCQ */
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};
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static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
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742, /* Group 0 */
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0, /* Group 1 */
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742, /* Public Max */
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0, /* WP threshold */
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};
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static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
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[RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
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&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
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[RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
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&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
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[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
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RTW89_HCIFC_POH},
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[RTW89_QTA_INVALID] = {NULL},
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};
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static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size22_v1,
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&rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
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&rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
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&rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
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&rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
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&rtw89_mac_size.dle_input28},
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[RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size22_v1,
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&rtw89_mac_size.ple_size29_v1, &rtw89_mac_size.wde_qt23_v1,
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&rtw89_mac_size.wde_qt23_v1, &rtw89_mac_size.ple_qt64_v2,
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&rtw89_mac_size.ple_qt65_v2, &rtw89_mac_size.ple_rsvd_qt9,
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&rtw89_mac_size.rsvd0_size17, &rtw89_mac_size.rsvd1_size3,
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&rtw89_mac_size.dle_input28},
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[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18_v1,
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&rtw89_mac_size.ple_size22_v1, &rtw89_mac_size.wde_qt3,
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&rtw89_mac_size.wde_qt3, &rtw89_mac_size.ple_qt5_v2,
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&rtw89_mac_size.ple_qt47_v2, &rtw89_mac_size.ple_rsvd_qt1,
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&rtw89_mac_size.rsvd0_size6, &rtw89_mac_size.rsvd1_size2,
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&rtw89_mac_size.dle_input3},
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[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
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NULL},
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};
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static const struct rtw89_hfc_ch_cfg rtw8922ds_hfc_chcfg_pcie[] = {
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{2, 603, 0}, /* ACH 0 */
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{0, 601, 0}, /* ACH 1 */
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{2, 603, 0}, /* ACH 2 */
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@ -40,24 +96,24 @@ static const struct rtw89_hfc_ch_cfg rtw8922d_hfc_chcfg_pcie[] = {
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{0, 0, 0}, /* GCQ */
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};
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static const struct rtw89_hfc_pub_cfg rtw8922d_hfc_pubcfg_pcie = {
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static const struct rtw89_hfc_pub_cfg rtw8922ds_hfc_pubcfg_pcie = {
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613, /* Group 0 */
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0, /* Group 1 */
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613, /* Public Max */
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0, /* WP threshold */
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};
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static const struct rtw89_hfc_param_ini rtw8922d_hfc_param_ini_pcie[] = {
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[RTW89_QTA_SCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
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static const struct rtw89_hfc_param_ini rtw8922ds_hfc_param_ini_pcie[] = {
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[RTW89_QTA_SCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
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&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
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[RTW89_QTA_DBCC] = {rtw8922d_hfc_chcfg_pcie, &rtw8922d_hfc_pubcfg_pcie,
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[RTW89_QTA_DBCC] = {rtw8922ds_hfc_chcfg_pcie, &rtw8922ds_hfc_pubcfg_pcie,
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&rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
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[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
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RTW89_HCIFC_POH},
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[RTW89_QTA_INVALID] = {NULL},
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};
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static const struct rtw89_dle_mem rtw8922d_dle_mem_pcie[] = {
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static const struct rtw89_dle_mem rtw8922ds_dle_mem_pcie[] = {
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[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size16_v1,
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&rtw89_mac_size.ple_size20_v1, &rtw89_mac_size.wde_qt19_v1,
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&rtw89_mac_size.wde_qt19_v1, &rtw89_mac_size.ple_qt44_v2,
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@ -3306,11 +3362,16 @@ static const struct rtw89_fw_def rtw8922de_vs_fw_def = {
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.fw_b_aid = RTL8922D_AID7060,
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};
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static const struct rtw89_qta_def rtw8922ds_qta_def = {
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.hfc_param_ini = {rtw8922ds_hfc_param_ini_pcie, NULL, NULL},
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.dle_mem = {rtw8922ds_dle_mem_pcie, NULL, NULL, NULL},
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};
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const struct rtw89_chip_variant rtw8922de_vs_variant = {
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.no_mcs_12_13 = true,
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.fw_min_ver_code = RTW89_FW_VER_CODE(0, 0, 0, 0),
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.fw_def_override = &rtw8922de_vs_fw_def,
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.qta_def_override = NULL,
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.qta_def_override = &rtw8922ds_qta_def,
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};
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EXPORT_SYMBOL(rtw8922de_vs_variant);
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