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Merge branch 'pci/iommu'
- Allow PASID on fake PCIe devices, e.g., HiSilicon KunPeng920 and KunPeng930 AMBA devices, without TLP prefixes (Zhangfei Gao) - Allow SVA / dma-can-stall on fake PCIe devices (Zhangfei Gao) * pci/iommu: PCI: Set dma-can-stall for HiSilicon chips PCI: Allow PASID on fake PCIe devices without TLP prefixes
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commit
9d102c7437
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@ -376,7 +376,7 @@ int pci_enable_pasid(struct pci_dev *pdev, int features)
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if (WARN_ON(pdev->pasid_enabled))
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return -EBUSY;
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if (!pdev->eetlp_prefix_path)
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if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp)
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return -EINVAL;
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if (!pasid)
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@ -1821,6 +1821,45 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
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/*
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* HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
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* actually on the AMBA bus. These fake PCI devices can support SVA via
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* SMMU stall feature, by setting dma-can-stall for ACPI platforms.
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*
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* Normally stalling must not be enabled for PCI devices, since it would
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* break the PCI requirement for free-flowing writes and may lead to
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* deadlock. We expect PCI devices to support ATS and PRI if they want to
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* be fault-tolerant, so there's no ACPI binding to describe anything else,
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* even when a "PCI" device turns out to be a regular old SoC device
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* dressed up as a RCiEP and normal rules don't apply.
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*/
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static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
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{
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struct property_entry properties[] = {
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PROPERTY_ENTRY_BOOL("dma-can-stall"),
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{},
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};
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if (pdev->revision != 0x21 && pdev->revision != 0x30)
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return;
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pdev->pasid_no_tlp = 1;
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/*
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* Set the dma-can-stall property on ACPI platforms. Device tree
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* can set it directly.
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*/
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if (!pdev->dev.of_node &&
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device_add_properties(&pdev->dev, properties))
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pci_warn(pdev, "could not add stall property");
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
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/*
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* It's possible for the MSI to get corrupted if SHPC and ACPI are used
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* together on certain PXH-based systems.
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@ -388,6 +388,7 @@ struct pci_dev {
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supported from root to here */
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u16 l1ss; /* L1SS Capability pointer */
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#endif
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unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
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unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
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pci_channel_state_t error_state; /* Current connectivity state */
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