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riscv/futex: Optimize atomic cmpxchg

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Remove redundant release/acquire barriers, optimizing the lr/sc sequence
to provide conditional RCsc synchronization, per the RVWMO.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241113183321.491113-1-dave@stgolabs.net
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Davidlohr Bueso 2024-11-13 10:33:21 -08:00 committed by Palmer Dabbelt
parent 0207244ea0
commit 9d0593da94
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1 changed files with 1 additions and 1 deletions
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arch/riscv/include/asm/futex.h
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@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
__enable_user_access();
__asm__ __volatile__ (
"1: lr.w.aqrl %[v],%[u] \n"
"1: lr.w %[v],%[u] \n"
" bne %[v],%z[ov],3f \n"
"2: sc.w.aqrl %[t],%z[nv],%[u] \n"
" bnez %[t],1b \n"