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m68k: mcf5441x: add CCR MISCCR2 bitfields

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Add CCR MISCCR2 register bitfields.

Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
This commit is contained in:
Angelo Dureghello 2026-06-10 22:35:10 +02:00 committed by Greg Ungerer
parent 8ccdac070d
commit 9cacf00c83
1 changed files with 17 additions and 0 deletions
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17
arch/m68k/include/asm/m5441xsim.h
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@ -8,6 +8,8 @@
#ifndef m5441xsim_h
#define m5441xsim_h
#include <linux/bits.h>
#define CPU_NAME "COLDFIRE(m5441x)"
#define CPU_INSTR_PER_JIFFY 2
#define MCF_BUSCLK (MCF_CLK / 2)
@ -145,6 +147,21 @@
#define MCF_CCM_SBFCR 0xec090022
#define MCF_CCM_FNACR 0xec090024
/* Bit definitions and macros for MCF_CCM_MISCCR2 */
#define MCF_CCM_MISCCR2_ULPI BIT(0)
#define MCF_CCM_MISCCR2_FB_HALF BIT(1)
#define MCF_CCM_MISCCR2_ADC3_EN BIT(2)
#define MCF_CCM_MISCCR2_ADC7_EN BIT(3)
#define MCF_CCM_MISCCR2_ADC_EN BIT(4)
#define MCF_CCM_MISCCR2_DAC0_SEL BIT(5)
#define MCF_CCM_MISCCR2_DAC1_SEL BIT(6)
#define MCF_CCM_MISCCR2_DCC_BYP BIT(7)
#define MCF_CCM_MISCCR2_PLL_MODE GENMASK(10, 8)
#define MCF_CCM_MISCCR2_SWT_SCR BIT(12)
#define MCF_CCM_MISCCR2_RGPIO_HALF BIT(13)
#define MCF_CCM_MISCCR2_DDR2_CLK BIT(14)
#define MCF_CCM_MISCCR2_EXTCLK_BYP BIT(15)
/*
* UART module.
*/