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A fix for the v3d register readout, and two compilation fixes for

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rockchip.
 -----BEGIN PGP SIGNATURE-----
 
 iHQEABYKAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCZZ+9vAAKCRDj7w1vZxhR
 xVoyAP4/4GH+JgLrj0pQwgY37Ifu1XlwiFJPSoTj9DSdrm3jEgD2Kuh5iXCF1Z1B
 cFL1ZTCfIX7g3VOYTkkvOHxDg7SkDA==
 =+wkK
 -----END PGP SIGNATURE-----

Merge tag 'drm-misc-next-fixes-2024-01-11' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

A fix for the v3d register readout, and two compilation fixes for
rockchip.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maxime Ripard <mripard@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/warlsyhbwarbezejzokxvrpnmvoaajonj6khjobvnfrhttrsks@fqoeqrjrct6l
This commit is contained in:
Dave Airlie 2024-01-15 10:09:33 +10:00
commit 9caaeb0901
2 changed files with 11 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@ -35,7 +35,6 @@
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop2.h"
#include "rockchip_rgb.h"
@ -1681,7 +1680,6 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
unsigned long dclk_core_rate = v_pixclk >> 2;
unsigned long dclk_rate = v_pixclk;
unsigned long dclk_out_rate;
unsigned long if_dclk_rate;
unsigned long if_pixclk_rate;
int K = 1;
@ -1696,8 +1694,8 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
}
if_pixclk_rate = (dclk_core_rate << 1) / K;
if_dclk_rate = dclk_core_rate / K;
/*
* if_dclk_rate = dclk_core_rate / K;
* *if_pixclk_div = dclk_rate / if_pixclk_rate;
* *if_dclk_div = dclk_rate / if_dclk_rate;
*/

20
drivers/gpu/drm/v3d/v3d_debugfs.c
View File

@ -62,9 +62,9 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {
REGDEF(33, 71, V3D_PTB_BPCA),
REGDEF(33, 71, V3D_PTB_BPCS),
REGDEF(33, 41, V3D_GMP_STATUS(33)),
REGDEF(33, 41, V3D_GMP_CFG(33)),
REGDEF(33, 41, V3D_GMP_VIO_ADDR(33)),
REGDEF(33, 42, V3D_GMP_STATUS(33)),
REGDEF(33, 42, V3D_GMP_CFG(33)),
REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
REGDEF(33, 71, V3D_ERR_FDBGO),
REGDEF(33, 71, V3D_ERR_FDBGB),
@ -74,13 +74,13 @@ static const struct v3d_reg_def v3d_core_reg_defs[] = {
static const struct v3d_reg_def v3d_csd_reg_defs[] = {
REGDEF(41, 71, V3D_CSD_STATUS),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),