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arm64: dts: st: add power domain on stm32mp25

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Add power domains on STM32MP25x SoC for supported low power modes:
- CPU_PD0/1: domain for idle of each core Cortex A35 (CStop)
- CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when
  the Cortex A35 cluster and each device assigned to CPU1=CA35
  are deactivated
- RET_PD: D1 domain retention (VDDCore is reduced) to support
          the LPLV-Stop1 mode

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Patrick Delaunay 2024-04-25 17:45:55 +02:00 committed by Alexandre Torgue
parent 624aa659af
commit 9c8d852dab
2 changed files with 25 additions and 0 deletions
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16
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@ -20,6 +20,8 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
};
};
@ -90,6 +92,20 @@ intc: interrupt-controller@4ac00000 {
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: power-domain-cluster {
#power-domain-cells = <0>;
power-domains = <&RET_PD>;
};
RET_PD: power-domain-retention {
#power-domain-cells = <0>;
};
};
timer {

9
arch/arm64/boot/dts/st/stm32mp253.dtsi
View File

@ -12,6 +12,8 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <1>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
};
};
@ -21,6 +23,13 @@ arm-pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
psci {
CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
};
timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,