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Renesas driver updates for v6.15

Browse Source 
- Add a driver for the System Controller on RZ/G3S, RZ/G3E, and
     RZ/V2H.
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Merge tag 'renesas-drivers-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.15

  - Add a driver for the System Controller on RZ/G3S, RZ/G3E, and
    RZ/V2H.

* tag 'renesas-drivers-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: r9a09g057-sys: Add a callback to print SoC-specific extra features
  soc: renesas: rz-sysc: Move RZ/V2H SoC detection to the SYS driver
  soc: renesas: rz-sysc: Add support for RZ/G3E family
  soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver
  soc: renesas: Add SYSC driver for Renesas RZ family

Link: https://lore.kernel.org/r/cover.1740156741.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-06 17:01:02 +01:00
commit 9c83645c9c
8 changed files with 363 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/soc/renesas/Kconfig
View File

@ -334,6 +334,7 @@ config ARCH_R9A07G054
config ARCH_R9A08G045
bool "ARM64 Platform support for RZ/G3S"
select ARCH_RZG2L
select SYSC_R9A08G045
help
This enables support for the Renesas RZ/G3S SoC variants.
@ -347,12 +348,14 @@ config ARCH_R9A09G011
config ARCH_R9A09G047
bool "ARM64 Platform support for RZ/G3E"
select SYS_R9A09G047
help
This enables support for the Renesas RZ/G3E SoC variants.
config ARCH_R9A09G057
bool "ARM64 Platform support for RZ/V2H(P)"
select RENESAS_RZV2H_ICU
select SYS_R9A09G057
help
This enables support for the Renesas RZ/V2H(P) SoC variants.
@ -383,4 +386,19 @@ config PWC_RZV2M
config RST_RCAR
bool "Reset Controller support for R-Car" if COMPILE_TEST
config SYSC_RZ
bool "System controller for RZ SoCs" if COMPILE_TEST
config SYSC_R9A08G045
bool "Renesas RZ/G3S System controller support" if COMPILE_TEST
select SYSC_RZ
config SYS_R9A09G047
bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
select SYSC_RZ
config SYS_R9A09G057
bool "Renesas RZ/V2H System controller support" if COMPILE_TEST
select SYSC_RZ
endif # SOC_RENESAS

4
drivers/soc/renesas/Makefile
View File

@ -6,7 +6,11 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
ifdef CONFIG_SMP
obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
endif
obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o
obj-$(CONFIG_SYS_R9A09G047) += r9a09g047-sys.o
obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o
# Family
obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o
obj-$(CONFIG_RST_RCAR) += rcar-rst.o
obj-$(CONFIG_SYSC_RZ) += rz-sysc.o

23
drivers/soc/renesas/r9a08g045-sysc.c Normal file
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@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G3S System controller driver
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#include <linux/bits.h>
#include <linux/init.h>
#include "rz-sysc.h"
static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = {
.family = "RZ/G3S",
.id = 0x85e0447,
.devid_offset = 0xa04,
.revision_mask = GENMASK(31, 28),
.specific_id_mask = GENMASK(27, 0),
};
const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
.soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
};

67
drivers/soc/renesas/r9a09g047-sys.c Normal file
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@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/G3E System controller (SYS) driver
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include "rz-sysc.h"
/* Register Offsets */
#define SYS_LSI_MODE 0x300
/*
* BOOTPLLCA[1:0]
* [0,0] => 1.1GHZ
* [0,1] => 1.5GHZ
* [1,0] => 1.6GHZ
* [1,1] => 1.7GHZ
*/
#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
#define SYS_LSI_PRR 0x308
#define SYS_LSI_PRR_CA55_DIS BIT(8)
#define SYS_LSI_PRR_NPU_DIS BIT(1)
static void rzg3e_sys_print_id(struct device *dev,
void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr)
{
bool is_quad_core, npu_enabled;
u32 prr_val, mode_val;
prr_val = readl(sysc_base + SYS_LSI_PRR);
mode_val = readl(sysc_base + SYS_LSI_MODE);
/* Check CPU and NPU configuration */
is_quad_core = !(prr_val & SYS_LSI_PRR_CA55_DIS);
npu_enabled = !(prr_val & SYS_LSI_PRR_NPU_DIS);
dev_info(dev, "Detected Renesas %s Core %s %s Rev %s%s\n",
is_quad_core ? "Quad" : "Dual", soc_dev_attr->family,
soc_dev_attr->soc_id, soc_dev_attr->revision,
npu_enabled ? " with Ethos-U55" : "");
/* Check CA55 PLL configuration */
if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
}
static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initconst = {
.family = "RZ/G3E",
.id = 0x8679447,
.devid_offset = 0x304,
.revision_mask = GENMASK(31, 28),
.specific_id_mask = GENMASK(27, 0),
.print_id = rzg3e_sys_print_id,
};
const struct rz_sysc_init_data rzg3e_sys_init_data = {
.soc_id_init_data = &rzg3e_sys_soc_id_init_data,
};

67
drivers/soc/renesas/r9a09g057-sys.c Normal file
View File

@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ/V2H System controller (SYS) driver
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include "rz-sysc.h"
/* Register Offsets */
#define SYS_LSI_MODE 0x300
/*
* BOOTPLLCA[1:0]
* [0,0] => 1.1GHZ
* [0,1] => 1.5GHZ
* [1,0] => 1.6GHZ
* [1,1] => 1.7GHZ
*/
#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
#define SYS_LSI_MODE_CA55_1_7GHZ 0x3
#define SYS_LSI_PRR 0x308
#define SYS_LSI_PRR_GPU_DIS BIT(0)
#define SYS_LSI_PRR_ISP_DIS BIT(4)
static void rzv2h_sys_print_id(struct device *dev,
void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr)
{
bool gpu_enabled, isp_enabled;
u32 prr_val, mode_val;
prr_val = readl(sysc_base + SYS_LSI_PRR);
mode_val = readl(sysc_base + SYS_LSI_MODE);
/* Check GPU and ISP configuration */
gpu_enabled = !(prr_val & SYS_LSI_PRR_GPU_DIS);
isp_enabled = !(prr_val & SYS_LSI_PRR_ISP_DIS);
dev_info(dev, "Detected Renesas %s %s Rev %s%s%s\n",
soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision,
gpu_enabled ? " with GE3D (Mali-G31)" : "",
isp_enabled ? " with ISP (Mali-C55)" : "");
/* Check CA55 PLL configuration */
if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
}
static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = {
.family = "RZ/V2H",
.id = 0x847a447,
.devid_offset = 0x304,
.revision_mask = GENMASK(31, 28),
.specific_id_mask = GENMASK(27, 0),
.print_id = rzv2h_sys_print_id,
};
const struct rz_sysc_init_data rzv2h_sys_init_data = {
.soc_id_init_data = &rzv2h_sys_soc_id_init_data,
};

33
drivers/soc/renesas/renesas-soc.c
View File

@ -71,14 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
.name = "RZ/G2UL",
};
static const struct renesas_family fam_rzg3s __initconst __maybe_unused = {
.name = "RZ/G3S",
};
static const struct renesas_family fam_rzv2h __initconst __maybe_unused = {
.name = "RZ/V2H",
};
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
@ -176,16 +168,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
.id = 0x8450447,
};
static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = {
.family = &fam_rzg3s,
.id = 0x85e0447,
};
static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = {
.family = &fam_rzv2h,
.id = 0x847a447,
};
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
@ -289,7 +271,6 @@ static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
.id = 0x37,
};
static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R7S72100
{ .compatible = "renesas,r7s72100", .data = &soc_rz_a1h },
@ -410,15 +391,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R9A07G054
{ .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l },
#endif
#ifdef CONFIG_ARCH_R9A08G045
{ .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s },
#endif
#ifdef CONFIG_ARCH_R9A09G011
{ .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m },
#endif
#ifdef CONFIG_ARCH_R9A09G057
{ .compatible = "renesas,r9a09g057", .data = &soc_rz_v2h },
#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
@ -444,11 +419,6 @@ static const struct renesas_id id_rzg2l __initconst = {
.mask = 0xfffffff,
};
static const struct renesas_id id_rzv2h __initconst = {
.offset = 0x304,
.mask = 0xfffffff,
};
static const struct renesas_id id_rzv2m __initconst = {
.offset = 0x104,
.mask = 0xff,
@ -466,7 +436,6 @@ static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m },
{ .compatible = "renesas,r9a09g057-sys", .data = &id_rzv2h },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
};
@ -531,7 +500,7 @@ static int __init renesas_soc_init(void)
eslo = product & 0xf;
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u",
eshi, eslo);
} else if (id == &id_rzg2l || id == &id_rzv2h) {
} else if (id == &id_rzg2l) {
eshi = ((product >> 28) & 0x0f);
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u",
eshi);

137
drivers/soc/renesas/rz-sysc.c Normal file
View File

@ -0,0 +1,137 @@
// SPDX-License-Identifier: GPL-2.0
/*
* RZ System controller driver
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/sys_soc.h>
#include "rz-sysc.h"
#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
/**
* struct rz_sysc - RZ SYSC private data structure
* @base: SYSC base address
* @dev: SYSC device pointer
*/
struct rz_sysc {
void __iomem *base;
struct device *dev;
};
static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match)
{
const struct rz_sysc_init_data *sysc_data = match->data;
const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data;
struct soc_device_attribute *soc_dev_attr;
const char *soc_id_start, *soc_id_end;
u32 val, revision, specific_id;
struct soc_device *soc_dev;
char soc_id[32] = {0};
size_t size;
soc_id_start = strchr(match->compatible, ',') + 1;
soc_id_end = strchr(match->compatible, '-');
size = soc_id_end - soc_id_start + 1;
if (size > 32)
size = sizeof(soc_id);
strscpy(soc_id, soc_id_start, size);
soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
return -ENOMEM;
soc_dev_attr->family = devm_kstrdup(sysc->dev, soc_data->family, GFP_KERNEL);
if (!soc_dev_attr->family)
return -ENOMEM;
soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL);
if (!soc_dev_attr->soc_id)
return -ENOMEM;
val = readl(sysc->base + soc_data->devid_offset);
revision = field_get(soc_data->revision_mask, val);
specific_id = field_get(soc_data->specific_id_mask, val);
soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision);
if (!soc_dev_attr->revision)
return -ENOMEM;
if (soc_data->id && specific_id != soc_data->id) {
dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id);
return -ENODEV;
}
/* Try to call SoC-specific device identification */
if (soc_data->print_id) {
soc_data->print_id(sysc->dev, sysc->base, soc_dev_attr);
} else {
dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n",
soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision);
}
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev))
return PTR_ERR(soc_dev);
return 0;
}
static const struct of_device_id rz_sysc_match[] = {
#ifdef CONFIG_SYSC_R9A08G045
{ .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },
#endif
#ifdef CONFIG_SYS_R9A09G047
{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data },
#endif
#ifdef CONFIG_SYS_R9A09G057
{ .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data },
#endif
{ }
};
MODULE_DEVICE_TABLE(of, rz_sysc_match);
static int rz_sysc_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct rz_sysc *sysc;
match = of_match_node(rz_sysc_match, dev->of_node);
if (!match)
return -ENODEV;
sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL);
if (!sysc)
return -ENOMEM;
sysc->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sysc->base))
return PTR_ERR(sysc->base);
sysc->dev = dev;
return rz_sysc_soc_init(sysc, match);
}
static struct platform_driver rz_sysc_driver = {
.driver = {
.name = "renesas-rz-sysc",
.suppress_bind_attrs = true,
.of_match_table = rz_sysc_match
},
.probe = rz_sysc_probe
};
static int __init rz_sysc_init(void)
{
return platform_driver_register(&rz_sysc_driver);
}
subsys_initcall(rz_sysc_init);
MODULE_DESCRIPTION("Renesas RZ System Controller Driver");
MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
MODULE_LICENSE("GPL");

46
drivers/soc/renesas/rz-sysc.h Normal file
View File

@ -0,0 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Renesas RZ System Controller
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#ifndef __SOC_RENESAS_RZ_SYSC_H__
#define __SOC_RENESAS_RZ_SYSC_H__
#include <linux/device.h>
#include <linux/sys_soc.h>
#include <linux/types.h>
/**
* struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data
* @family: RZ SoC family
* @id: RZ SoC expected ID
* @devid_offset: SYSC SoC ID register offset
* @revision_mask: SYSC SoC ID revision mask
* @specific_id_mask: SYSC SoC ID specific ID mask
* @print_id: print SoC-specific extended device identification
*/
struct rz_sysc_soc_id_init_data {
const char * const family;
u32 id;
u32 devid_offset;
u32 revision_mask;
u32 specific_id_mask;
void (*print_id)(struct device *dev, void __iomem *sysc_base,
struct soc_device_attribute *soc_dev_attr);
};
/**
* struct rz_sysc_init_data - RZ SYSC initialization data
* @soc_id_init_data: RZ SYSC SoC ID initialization data
*/
struct rz_sysc_init_data {
const struct rz_sysc_soc_id_init_data *soc_id_init_data;
};
extern const struct rz_sysc_init_data rzg3e_sys_init_data;
extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
extern const struct rz_sysc_init_data rzv2h_sys_init_data;
#endif /* __SOC_RENESAS_RZ_SYSC_H__ */