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net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC, add MT7531_QRY_FFP
The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and MT7531/MT7988. Add MT7530 prefix to these definitions, and define the IGMP/MLD Query Frame Flooding Ports mask for MT7531. Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK. Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as macros. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arınç ÜNAL
David S. Miller
parent
7603a0c7d2
commit
9c7401dc1b
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@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
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PORT_SPEC_TAG);
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/* Enable flooding on the CPU port */
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mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
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mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
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UNU_FFP(BIT(port)));
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/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
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@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
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flags.val & BR_LEARNING ? 0 : SA_DIS);
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if (flags.mask & BR_FLOOD)
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mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
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mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
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flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
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if (flags.mask & BR_MCAST_FLOOD)
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mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
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mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
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flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
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if (flags.mask & BR_BCAST_FLOOD)
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mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
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mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
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flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
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return 0;
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@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int port,
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return 0;
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}
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static int mt753x_mirror_port_get(unsigned int id, u32 val)
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{
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return (id == ID_MT7531 || id == ID_MT7988) ?
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MT7531_MIRROR_PORT_GET(val) :
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MIRROR_PORT(val);
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}
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static int mt753x_mirror_port_set(unsigned int id, u32 val)
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{
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return (id == ID_MT7531 || id == ID_MT7988) ?
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MT7531_MIRROR_PORT_SET(val) :
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MIRROR_PORT(val);
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}
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static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
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struct dsa_mall_mirror_tc_entry *mirror,
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bool ingress, struct netlink_ext_ack *extack)
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@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
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val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
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/* MT7530 only supports one monitor port */
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monitor_port = mt753x_mirror_port_get(priv->id, val);
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monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
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if (val & MT753X_MIRROR_EN(priv->id) &&
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monitor_port != mirror->to_local_port)
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return -EEXIST;
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val |= MT753X_MIRROR_EN(priv->id);
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val &= ~MT753X_MIRROR_MASK(priv->id);
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val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
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val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
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val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
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mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
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val = mt7530_read(priv, MT7530_PCR_P(port));
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@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *ds)
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mt7530_mib_reset(ds);
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/* Disable flooding on all ports */
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mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
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mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
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UNU_FFP_MASK);
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for (i = 0; i < MT7530_NUM_PORTS; i++) {
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@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_switch *ds,
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else
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priv->active_cpu_ports &= ~mask;
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if (priv->active_cpu_ports)
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val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
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if (priv->active_cpu_ports) {
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val = MT7530_CPU_EN |
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MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
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}
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mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
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mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
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}
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static int mt7988_setup(struct dsa_switch *ds)
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@ -36,36 +36,55 @@ enum mt753x_id {
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#define MT753X_AGC 0xc
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#define LOCAL_EN BIT(7)
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/* Registers to mac forward control for unknown frames */
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#define MT7530_MFC 0x10
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#define BC_FFP(x) (((x) & 0xff) << 24)
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#define BC_FFP_MASK BC_FFP(~0)
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#define UNM_FFP(x) (((x) & 0xff) << 16)
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#define UNM_FFP_MASK UNM_FFP(~0)
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#define UNU_FFP(x) (((x) & 0xff) << 8)
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#define UNU_FFP_MASK UNU_FFP(~0)
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#define CPU_EN BIT(7)
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#define CPU_PORT_MASK GENMASK(6, 4)
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#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
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#define MIRROR_EN BIT(3)
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#define MIRROR_PORT(x) ((x) & 0x7)
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#define MIRROR_MASK 0x7
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/* Register for MAC forward control */
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#define MT753X_MFC 0x10
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#define BC_FFP_MASK GENMASK(31, 24)
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#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
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#define UNM_FFP_MASK GENMASK(23, 16)
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#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
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#define UNU_FFP_MASK GENMASK(15, 8)
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#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
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#define MT7530_CPU_EN BIT(7)
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#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
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#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
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#define MT7530_MIRROR_EN BIT(3)
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#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
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#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
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#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
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#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
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#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
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/* Registers for CPU forward control */
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/* Register for CPU forward control */
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#define MT7531_CFC 0x4
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#define MT7531_MIRROR_EN BIT(19)
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#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
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#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
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#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
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#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
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#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
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#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
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#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
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#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
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#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
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MT7531_CFC : MT7530_MFC)
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#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
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MT7531_MIRROR_EN : MIRROR_EN)
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#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
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MT7531_MIRROR_MASK : MIRROR_MASK)
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#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
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id == ID_MT7988) ? \
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MT7531_CFC : MT753X_MFC)
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#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
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id == ID_MT7988) ? \
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MT7531_MIRROR_EN : MT7530_MIRROR_EN)
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#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
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id == ID_MT7988) ? \
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MT7531_MIRROR_PORT_MASK : \
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MT7530_MIRROR_PORT_MASK)
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#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
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id == ID_MT7988) ? \
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MT7531_MIRROR_PORT_GET(val) : \
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MT7530_MIRROR_PORT_GET(val))
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#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
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id == ID_MT7988) ? \
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MT7531_MIRROR_PORT_SET(val) : \
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MT7530_MIRROR_PORT_SET(val))
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/* Register for BPDU and PAE frame control */
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#define MT753X_BPC 0x24
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