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gpio: ppc44x: fix undefined behavior in GPIO_MASK2 macro

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Shifting a 32-bit unsigned integer by 32 or more places is undefined
behavior in C. GPIO_MASK2 computes its shift amount as (gpio) * 2, and
for pins 16-31 in the OSRH/TSRH bank this yields shifts of 32-62.
While this happens to work on PowerPC because slw masks the shift count
to the low 5 bits, compilers performing value-range propagation may
assume the else branch is unreachable and optimize it away, or may
evaluate the shift as zero on other architectures via COMPILE_TEST.

Mask gpio to the 16-pin bank index so the shift stays within [0, 30].
The registers are banked (OSRL/TSRL for gpio 0-15, OSRH/TSRH for
gpio 16-31) with an identical 2-bit-per-pin layout from MSB to LSB,
so masking to the within-bank index preserves the intended behavior.

Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/20260803223539.86303-8-rosenp@gmail.com
This commit is contained in:
Rosen Penev 2026-08-03 15:35:38 -07:00 committed by Madhavan Srinivasan
parent 595f5f25a9
commit 9c4d539d11
1 changed files with 1 additions and 1 deletions
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2
drivers/gpio/gpio-ppc44x.c
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@ -19,7 +19,7 @@
#include <linux/platform_device.h>
#define GPIO_MASK(gpio) (0x80000000 >> (gpio))
#define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2))
#define GPIO_MASK2(gpio) (0xc0000000 >> (((gpio) % 16) * 2))
/* Physical GPIO register layout */
struct ppc44x_gpio {