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drm/amdgpu/vcn: make powergating status per instance

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Store it per instance so we can track it per instance.

v2: index instances directly on vcn1.0 and 2.0 to make
it clear that they only support a single instance (Lijo)

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2024-11-13 15:28:41 -05:00
parent bee48570cf
commit 9bf9442051
11 changed files with 248 additions and 144 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
View File

@ -320,6 +320,7 @@ struct amdgpu_vcn_inst {
uint32_t vcn_codec_disable_mask;
atomic_t total_submission_cnt;
struct mutex vcn_pg_lock;
enum amd_powergating_state cur_state;
struct delayed_work idle_work;
};
@ -330,7 +331,6 @@ struct amdgpu_vcn_ras {
struct amdgpu_vcn {
unsigned fw_version;
unsigned num_enc_rings;
enum amd_powergating_state cur_state;
bool indirect_sram;
uint8_t num_vcn_inst;

6
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
View File

@ -280,7 +280,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
(adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
int ret;
struct amdgpu_device *adev = ip_block->adev;
if (state == adev->vcn.cur_state)
if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@ -1822,7 +1822,7 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v1_0_start(adev);
if (!ret)
adev->vcn.cur_state = state;
adev->vcn.inst[0].cur_state = state;
return ret;
}

11
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
View File

@ -316,8 +316,8 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
(adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
@ -1810,11 +1810,11 @@ static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
adev->vcn.inst[0].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.cur_state)
if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@ -1823,7 +1823,8 @@ static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v2_0_start(adev);
if (!ret)
adev->vcn.cur_state = state;
adev->vcn.inst[0].cur_state = state;
return ret;
}

51
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
View File

@ -95,8 +95,11 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
@ -397,9 +400,9 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
(adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, mmUVD_STATUS)))
vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
vcn_v2_5_set_powergating_state_inst(ip_block, AMD_PG_STATE_GATE, i);
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
@ -1808,27 +1811,39 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v2_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev))
return 0;
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v2_5_stop(adev, i);
else
ret = vcn_v2_5_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
if (amdgpu_sriov_vf(adev))
return 0;
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v2_5_stop(adev, i);
else
ret |= vcn_v2_5_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
ret |= vcn_v2_5_set_powergating_state_inst(ip_block,
state, i);
return ret;
}

49
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View File

@ -105,8 +105,11 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v3_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@ -430,9 +433,11 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
(adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v3_0_set_powergating_state_inst(ip_block,
AMD_PG_STATE_GATE,
i);
}
}
}
@ -2150,33 +2155,45 @@ static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
static int vcn_v3_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
int ret = 0;
/* for SRIOV, guest should not control VCN Power-gating
* MMSCH FW should control Power-gating and clock-gating
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
adev->vcn.inst[i].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.cur_state)
if (state == adev->vcn.inst[i].cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v3_0_stop(adev, i);
else
ret |= vcn_v3_0_start(adev, i);
}
if (state == AMD_PG_STATE_GATE)
ret = vcn_v3_0_stop(adev, i);
else
ret = vcn_v3_0_start(adev, i);
if (!ret)
adev->vcn.cur_state = state;
adev->vcn.inst[i].cur_state = state;
return ret;
}
static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
ret |= vcn_v3_0_set_powergating_state_inst(ip_block,
state, i);
return ret;
}

62
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
View File

@ -96,8 +96,11 @@ static int amdgpu_ih_clientid_vcns[] = {
static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
@ -367,9 +370,9 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
(adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
vcn_v4_0_set_powergating_state_inst(ip_block, AMD_PG_STATE_GATE, i);
}
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@ -2034,6 +2037,36 @@ static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v4_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
/* for SRIOV, guest should not control VCN Power-gating
* MMSCH FW should control Power-gating and clock-gating
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
adev->vcn.inst[i].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v4_0_stop(adev, i);
else
ret = vcn_v4_0_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
/**
* vcn_v4_0_set_powergating_state - set VCN block powergating state
*
@ -2048,27 +2081,8 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
/* for SRIOV, guest should not control VCN Power-gating
* MMSCH FW should control Power-gating and clock-gating
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v4_0_stop(adev, i);
else
ret |= vcn_v4_0_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
ret |= vcn_v4_0_set_powergating_state_inst(ip_block, state, i);
return ret;
}

67
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
View File

@ -87,8 +87,11 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_3_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
@ -351,11 +354,12 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE)
vcn_v4_0_3_set_powergating_state_inst(ip_block, AMD_PG_STATE_GATE, i);
}
return 0;
}
@ -1640,6 +1644,36 @@ static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v4_0_3_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
/* for SRIOV, guest should not control VCN Power-gating
* MMSCH FW should control Power-gating and clock-gating
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
adev->vcn.inst[i].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v4_0_3_stop(adev, i);
else
ret = vcn_v4_0_3_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
/**
* vcn_v4_0_3_set_powergating_state - set VCN block powergating state
*
@ -1649,32 +1683,13 @@ static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
* Set VCN block powergating state
*/
static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
/* for SRIOV, guest should not control VCN Power-gating
* MMSCH FW should control Power-gating and clock-gating
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v4_0_3_stop(adev, i);
else
ret |= vcn_v4_0_3_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
vcn_v4_0_3_set_powergating_state_inst(ip_block, state, i);
return ret;
}

48
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
View File

@ -95,8 +95,11 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);
@ -308,9 +311,9 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
(adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v4_0_5_set_powergating_state_inst(ip_block, AMD_PG_STATE_GATE, i);
}
}
}
@ -1522,6 +1525,27 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v4_0_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v4_0_5_stop(adev, i);
else
ret = vcn_v4_0_5_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
/**
* vcn_v4_0_5_set_powergating_state - set VCN block powergating state
*
@ -1531,23 +1555,13 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
* Set VCN block powergating state
*/
static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v4_0_5_stop(adev, i);
else
ret |= vcn_v4_0_5_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
vcn_v4_0_5_set_powergating_state_inst(ip_block, state, i);
return ret;
}

48
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
View File

@ -78,8 +78,11 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v5_0_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
@ -288,9 +291,9 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
(adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v5_0_0_set_powergating_state_inst(ip_block, AMD_PG_STATE_GATE, i);
}
}
}
@ -1262,6 +1265,27 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v5_0_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v5_0_0_stop(adev, i);
else
ret = vcn_v5_0_0_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
/**
* vcn_v5_0_0_set_powergating_state - set VCN block powergating state
*
@ -1271,23 +1295,13 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
* Set VCN block powergating state
*/
static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret |= vcn_v5_0_0_stop(adev, i);
else
ret |= vcn_v5_0_0_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
vcn_v5_0_0_set_powergating_state_inst(ip_block, state, i);
return ret;
}

40
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
View File

@ -40,8 +40,11 @@
static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v5_0_1_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i);
static int vcn_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
enum amd_powergating_state state);
static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring);
/**
@ -988,6 +991,27 @@ static int vcn_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
static int vcn_v5_0_1_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state,
int i)
{
struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v5_0_1_stop(adev, i);
else
ret = vcn_v5_0_1_start(adev, i);
if (!ret)
adev->vcn.inst[i].cur_state = state;
return ret;
}
/**
* vcn_v5_0_1_set_powergating_state - set VCN block powergating state
*
@ -1002,18 +1026,8 @@ static int vcn_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
struct amdgpu_device *adev = ip_block->adev;
int ret = 0, i;
if (state == adev->vcn.cur_state)
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (state == AMD_PG_STATE_GATE)
ret = vcn_v5_0_1_stop(adev, i);
else
ret = vcn_v5_0_1_start(adev, i);
}
if (!ret)
adev->vcn.cur_state = state;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
vcn_v5_0_1_set_powergating_state_inst(ip_block, state, i);
return ret;
}

8
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -2041,15 +2041,15 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
for (i = 0; i < adev->vcn.num_vcn_inst; i++)
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
smu_dpm_set_vcn_enable(smu, false, i);
adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;
}
smu_dpm_set_jpeg_enable(smu, false);
adev->jpeg.cur_state = AMD_PG_STATE_GATE;
smu_dpm_set_vpe_enable(smu, false);
smu_dpm_set_umsch_mm_enable(smu, false);
adev->vcn.cur_state = AMD_PG_STATE_GATE;
adev->jpeg.cur_state = AMD_PG_STATE_GATE;
if (!smu->pm_enabled)
return 0;