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Limit a register write width in altera_edac to avoid hw errors

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Merge tag 'edac_urgent_for_v6.16_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC fix from Borislav Petkov:
 "Limit a register write width in altera_edac to avoid hw errors"

* tag 'edac_urgent_for_v6.16_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/altera: Use correct write width with the INTTEST register
This commit is contained in:
Linus Torvalds 2025-06-01 08:58:31 -07:00
commit 9bebf9f9d5
1 changed files with 3 additions and 3 deletions
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6
drivers/edac/altera_edac.c
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@ -1746,9 +1746,9 @@ altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
local_irq_save(flags);
if (trig_type == ALTR_UE_TRIGGER_CHAR)
writel(priv->ue_set_mask, set_addr);
writew(priv->ue_set_mask, set_addr);
else
writel(priv->ce_set_mask, set_addr);
writew(priv->ce_set_mask, set_addr);
/* Ensure the interrupt test bits are set */
wmb();
@ -1778,7 +1778,7 @@ altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
local_irq_save(flags);
if (trig_type == ALTR_UE_TRIGGER_CHAR) {
writel(priv->ue_set_mask, set_addr);
writew(priv->ue_set_mask, set_addr);
} else {
/* Setup read/write of 4 bytes */
writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);