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dma: dma-axi-dmac: fix SW cyclic transfers
If 'hw_cyclic' is false we should still be able to do cyclic transfers in "software". That was not working for the case where 'desc->num_sgs' is 1 because 'chan->next_desc' is never set with the current desc which means that the cyclic transfer only runs once and in the next SOT interrupt we do nothing since vchan_next_desc() will return NULL. Fix it by setting 'chan->next_desc' as soon as we get a new desc via vchan_next_desc(). Fixes:0e3b67b348("dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller") Signed-off-by: Nuno Sá <nuno.sa@analog.com> base-commit:3980351785change-id: 20251104-axi-dmac-fixes-and-improvs-e3ad512a329c Acked-by: Michael Hennerich <michael.hennerich@analog.com> Link: https://patch.msgid.link/20251104-axi-dmac-fixes-and-improvs-v1-1-3e6fd9328f72@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -247,6 +247,7 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
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return;
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list_move_tail(&vdesc->node, &chan->active_descs);
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desc = to_axi_dmac_desc(vdesc);
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chan->next_desc = desc;
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}
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sg = &desc->sg[desc->num_submitted];
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@ -265,8 +266,6 @@ static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
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else
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chan->next_desc = NULL;
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flags |= AXI_DMAC_FLAG_LAST;
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} else {
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chan->next_desc = desc;
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}
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sg->hw->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);
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